UNIT 2 Data Flow description OBJECTIVES HDL Programming

UNIT 2: Data Flow description OBJECTIVES HDL Programming Fundamentals • Understand the concept of data flow description • Identify the basic statements and components of data flow • Review and understand the fundamentals of some digital logic systems such as half adder, 2 x 1 multiplexer, 2 x 2 combinational array multiplier, 2 -bit comparator, D-latch, ripple-carry adder, and carry-lookahead Adder.

2. 1 Highlights of Data Flow Description • Data flow description simulates the system by showing how the signal flows from the input of the system to its output. The Boolean function of the output or the logical structure of the system shows such signal flow. HDL Programming Fundamentals • Signal assignment statements are concurrent. At any simulation time, all signal assignment statements that have an event are executed concurrently.

2. 2 Structure of Data Flow Description Listing 2. 1 Example of HDL Data Flow Description. architecture dtfl_ex of system is begin O 1 <= I 1 and I 2; -- statement 1. O 2 <= I 1 xor I 2; -- statement 2. --Statements 1 and 2 are signal assignment statements end dtfl_ex; HDL Programming Fundamentals entity system is port (I 1, I 2 : in bit; O 1, O 2 : out bit); end;

2. 2. 1 Signal Declaration and Assignment Statements signal s 1, s 2: bit; See slide 4 HDL Programming Fundamentals 2. 2. 2 Concurrent Signal Assignment Statement All statements that have event (s) on the right hand side are executed concurrently

event I 2 event I 1 event 10 ns Calculate 0 and 1 =0 Assign 0 O 1 <= I 1 and I 2; Calculate 1 and 1 =1 Assign 1 Calculate 1 and 1 =1 O 1 <= I 1 and I 2 after 10 ns; Can you do the same for O 2? Assign 1 HDL Programming Fundamentals O 1

2. 2. 3 Constant Declaration and Assignment Statements Constant period: time : = 100 ns; HDL Programming Fundamentals

Example 2. 1 Data Flow Description of a Half Adder Listing 2. 2 HDL Programming Fundamentals

2. 2. 4 Assigning Delay Time to Signal Assignment Statement S 1 <= sel and b after 10 ns; ………(VHDL) assign #10 S 1 = sel & b …………(Verilog). HDL Programming Fundamentals The 10 in Verilog code is 10 screen units

Example 2. 2 2 x 1 Multiplexer with active low enable Y = (G and A and Gbar H L L Output Y L A B or (G and B and SEL); G is the invert of Gbar HDL Programming Fundamentals Input SEL X L H

library IEEE; use IEEE. STD_LOGIC_1164. ALL; entity mux 2 x 1 is port (A, B, SEL, Gbar: in std_logic; Y: out std_logic); end mux 2 x 1; HDL Programming Fundamentals architecture MUX_DF of mux 2 x 1 is signal S 1, S 2, S 3, S 4, S 5 : std_logic; Constant dly : time : = 7 ns; -- replace all 7 ns with dly. Begin -- Assume 7 nano seconds propagation delay -for all and, or, and not. st 1: Y <= S 4 or S 5 after 7 ns; st 2: S 4 <= A and S 2 and S 1 after 7 ns; st 3: S 5 <= B and S 3 and S 1 after 7 ns; st 4: S 2 <= not SEL after 7 ns; st 5: S 3 <= not S 2 after 7 ns; st 6: S 1 <= not Gbar after 7 ns; end MUX_DF;

2. 3 Data Type-Vectors signal a: bit_vector (3 downto 0)………. VHDL signal a: bit_vector (0 to 3)………. VHDL wire [0: 3] a…………. Verilog HDL Programming Fundamentals wire [3: 0] a…………. Verilog

Example 2. 3 2 x 2 Unsigned combinational array multiplier HDL Programming Fundamentals

Example 2. 3 2 x 2 Unsigned combinational array multiplier 0111 HDL Programming Fundamentals Downto versus to library IEEE; If P = 7, downto use IEEE. STD_LOGIC_1164. ALL; to 1110 entity mult_arry is port(a, b: in std_logic_vector(1 downto 0); P: out std_logic_vector (3 downto 0)); end mult_arry; architecture MULT_DF of mult_arry is begin --For simplicity propagation delay times are not considered -- in this example. P(0) <= a(0) and b(0); P(1) <= (a(0) and b(1)) xor (a(1) and b(0)); P(2) <= (a(1) and b(1)) xor ((a(0) and b(1)) and (a(1) and b(0))); P(3) <= (a(1) and b(1)) and ((a(0) and b(1))and (a(1) and b(0))); end MULT_DF;

Example 2. 4 D-Latch _ Q = EQ + ED Q current state 0 1 x x Next state Q+ 0 1 _ Qbar = Q Latch-level sensitive. When E=1, Q = D otherwise Q retains its previous value Flip-flop, edge sensitive. When edge of E, Q=D otherwise Q retains its previous value HDL Programming Fundamentals E 0 0 1 1 Inputs D x x 0 1

HDL Programming Fundamentals _ Qbar = Q _ Q = EQ + ED

architecture DL_Dt. Fl of D_Latch is constant Delay_Eor. D: Time: = 9 ns; constant Delay_inv : Time : = 1 ns; begin --Assume 9 nsec propagation delay time between E or D and Qbar; and 1 nsec -- between Qbar and Q. Qbar <=(D and E) nor (not E and Q)after Delay_Eor. D; Q <= not Qbar after Delay_inv; end DL_Dt. Fl; HDL Programming Fundamentals Example 2. 4 D-latch library IEEE; use IEEE. STD_LOGIC_1164. ALL; entity D_Latch is port (D, E: in std_logic; Q, Qbar: buffer std_logic); -- Q and Qbar are declared as buffer because they act as both input and --output, they appear on the right and left hand side of signal assignment --statements. inout or linkage could have been used instead of buffer. end D_Latch;

_ Qbar = Q HDL Programming Fundamentals _ Above waveform is for Q = EQ + ED , Compare between latch and Flip-Flop. What would be the waveform for FF?

In Class Practice 2. 2 Write a data-flow description (both VHDL and Verilog) of a system that has three 1 -bit inputs a(1), a (2), and a (3), and one 1 -bit output b. a(1) is the least significant bit. b is 1 only when {a(1)a(2)a(3)}= 1, 3, 6 or 7 (all in decimal), otherwise 0. Derive a minimized Boolean function of the system and write the data flow description. Simulate the system and verify it is working as designed. What is the function of this system? a(1) Output b 0 0 1 1 0 1 0 0 1 1 0 0 1 1 a(1) 0 The system is 2 x 1 multiplexer a(2) a(3) 1 2 X 1 MUX HDL Programming Fundamentals Input a(3) a(2) b

--Program for prob 2. 2 library IEEE; use IEEE. STD_LOGIC_1164. ALL; entity probl 2_2 is port ( a : in std_logic_vector (3 downto 1); b: out std_logic); architecture dataflow of probl 2_2 is begin b <= ((not a(3)) and a(1)) or (a(3) and a(2)); end dataflow ; --bit could have been used instead of std_logic. HDL Programming Fundamentals end probl 2_2; --Since no delay time is specified we wrote one Boolean equation of the system; if --delay time is required, we have to use intermediate signals to describe the invert -- of a 3, the “and”, and the “or”

Verilog 1. 3. 2 Structure of Verilog Module Verilog is case Sensitive A≠a ADDR ≠ ADDr 1. 3. 2. 1 Verilog Ports input: the port is an input port only, the port is read. output: the port is an output port. The port, in contrast to VHDL output port, may appear in both sides of the assignment statement. inout: the port can be used as both input and output. The inout port is representing a bidirectional buss. HDL Programming Fundamentals module half_adder (I 1, I 2, O 1, O 2); input I 1; input I 2; output O 1; output O 2; //Blank lines are allowed assign O 1 = I 1 ^ I 2; //statement 1 assign O 2 = I 1 & I 2; // statement 2 endmodule

module mux 2 x 1(A, B, SEL, Gbar, Y); input A, B, SEL, Gbar; output Y; wire S 1, S 2, S 3, S 4, S 5; /* Assume 7 time units delay for all and, or, not. In Verilog we can not use specific time units such as nano seconds, the delay here is expressed in simulation screen units. */ assign #7 Y = S 4 | S 5; // st 1. assign #7 S 4 = A & S 2 & S 1; // st 2 assign #7 S 5 = B & S 3 & S 1; //st 3 assign #7 S 2 = ~ SEL; //st 4 assign #7 S 3 = ~ S 2; //st 5 assign #7 S 1 = ~ Gbar; // st 6 endmodule As in VHDL, all signal assignment statements (st 1 -st 6) that have an event in the right hand side are executed concurrently. Execution is done, as in VHDL, in two phases: Calculate and Assign HDL Programming Fundamentals VHDL Commands or Components Verilog Counterpart entity module <= assign and, or, xor, not &, |, ^, ~ signal wire after # in, out, inout input, output, inout () []

HDL Programming Fundamentals b) Verilog 2 x 2 unsigned comb. Array multiplier (Listing 2. 4) module mult_arry(a, b, P); input [1: 0] a, b; output [3: 0] P; /*For simplicity, propagation delay times are not considered in this example. */ assign P[0] = a[0] & b[0]; assign P[1] = (a[0] & b[1]) ^ (a[1] & b[0]); assign P[2] = (a[1] & b[1]) ^ ((a[0] & b[1]) & (a[1] & b[0])); assign P[3] = (a[1] & b[1]) & ((a[0] & b[1])& (a[1] & b[0])); endmodule

In Class Practice 2. 2 Write a data-flow description (both VHDL and Verilog) of a system that has three 1 -bit inputs a(1), a (2), and a (3), and one 1 -bit output b. a(1) is the least significant bit. b is 1 only when {a(1)a(2)a(3)}= 1, 3, 6 or 7 (all in decimal), otherwise 0. Derive a minimized Boolean function of the system and write the data flow description. Simulate the system and verify it is working as designed. USE VERILOG HDL Programming Fundamentals module prob 2_2(a, b); input [3: 1]a; output b; assign b= (~a[3] & a[1]) | (a[3] & a[2]); endmodule

Example 2. 5 2 -bit Magnitude Comparator Listing 2. 6 Both VHDL and Verilog HDL Programming Fundamentals

Case Study 2. 1 Adders Listing 2. 7 HDL Programming Fundamentals Ripple Carry Adder

HDL Programming Fundamentals Look-ahead Adder

HDL Programming Fundamentals

HDL Programming Fundamentals

2. 4 Summary HDL Programming Fundamentals