UltraDeep submicron technology Etienne Sicard Insa etienne sicardinsatlse

Ultra-Deep submicron technology Etienne Sicard Insa etienne. sicard@insa-tlse. fr http: //intrage. insa-tlse. fr/~etienne E. Sicard - ultra deep submicron

Summary • Ultra-deep submicron technology • Specific features • Embedded Memory • Magnetic RAM • SOI • conclusion E. Sicard - ultra deep submicron

1. Ultra-deep submicron technology 2. 0 Micron Sub-micron 80286 80386 1. 0 Ultra Nano Deep-sub micron 486 pentium II 0. 3 0. 2 Pentium IV Itanium 0. 1 0. 05 0. 03 83 86 89 92 95 98 01 Year E. Sicard - ultra deep submicron 04 07

1. Ultra-deep submicron technology • Multiple technological options to optimize performance • Faster & bigger chips • Agreements to handle tremendous costs (ST, Philips, Motorola, TSMC) E. Sicard - ultra deep submicron

2. Specific features Multiple metal layers Stacked vias Low K dielectric to reduce couplings Copper to speed up signal transport High K dielectric to reduce leakage Improved tretch isolation Multiple MOS options E. Sicard - ultra deep submicron

2. Specific features • High Speed: normal MOS • Very high speed: critical path • Low leakage: for low power 3 -6 MOS options • High voltage: for I/Os • Double-gate: for embedded EEPROM • RF : optimized for GHz amplifiers E. Sicard - ultra deep submicron

2. Specific features Low Leakage Ultra High Speed EEProm High Voltage RF High Speed Application-oriented MOS device Same basic mechanism New physical properties in EEPROM and MRam E. Sicard - ultra deep submicron MRa m

2. Specific features 1. 2 V 2. 5 V 1. 2 V High Speed Low leakage 1. 2 V 2. 5 V High Voltage 2. 5 V 1. 8 V Example in 0. 12µm technology E. Sicard - ultra deep submicron

2. Specific features Option layer Simple access to low leakage, high voltage and isolated Pwell E. Sicard - ultra deep submicron Option layer properties

2. Specific features Low leakage High speed High voltage Simulation of the 3 MOS options E. Sicard - ultra deep submicron

2. Specific features Small Ion reduction Ioff ~10 n. A Ioff ~100 p. A Low leakage High speed Low leakage MOS has higher Vt, slight Ion reduction Low leakage MOS has 1/100 Ioff of high speed MOS E. Sicard - ultra deep submicron

2. Specific features 0. 1µm process (TSMC+ST+IBM+…) Each MOS is optimized for a target customer application Towards a world-wide standard process which will ease design E. Sicard - ultra deep submicron

3. Embedded Memory • 80% of a system-on-chip • Bottleneck for bandwidth Cmos Embedded memories Volatile e. DRAM SRAM Non volatile ROM EEPROM FRAM E. Sicard - ultra deep submicron

3. Embedded Memory CS CB Parasitic capacitance: 2 f. F Specific capacitance: 3 -30 f. F E. Sicard - ultra deep submicron

3. Embedded Memory Double-Gate MOS 2 nd Poly Floating Poly Used in EPROM, EEPROM and Flash memories E. Sicard - ultra deep submicron

3. Embedded Memory Double-Gate MOS Ids Single gate Double gate Vds Gate discharged Gate charged E. Sicard - ultra deep submicron

3. Embedded Memory Double-Gate MOS: write/erase by tunneling 0 V 12 V “Hot” electron Tunneling 0 Vdd “Cold” electron Tunneling 12 V Accelerate erase write Dense but slow E. Sicard - ultra deep submicron

4. Magnetic RAM Dense, fast, non-volatile: universal memory Silicium, Cobalt et Nikel 2 stage magnetic states A high magnetic field changes the state of the material E. Sicard - ultra deep submicron equal to I=5 m. A

4. Magnetic RAM Column i/2 Line i/4 i/2 Write Erase Principles: Write: i/2 on the line, i/2 on the column gives a current high enough to change the state Read: i/4 on the line, i/4 on the column and monitor the attenuation of current due to magnetic state Read E. Sicard - ultra deep submicron

5. Silicon-On-insulator The next major evolution? CMOS compatible Less distance between n. MOS and p. MOS Less capacitance Less leakage >50% faster circuits Fully or partially depleted? E. Sicard - ultra deep submicron Kink effect

6. Conclusion • The ultra-deep submicron technologies introduce new features • Low leakage MOS targeted for low power • High voltage MOS introduced for I/O interfacing • Double-poly MOS for EPROM/Flash memories • Embedded memory are key components for System-on-chip • Magnetic RAM to become the “universal memory” • SOI has many promising features, some design issues pending E. Sicard - ultra deep submicron