Ultra Low Power CMOS Design Ph D Dissertation

Ultra Low Power CMOS Design Ph. D. Dissertation Proposal Kyungseok Kim ECE Auburn Univ. Chair: Prof. Vishwani D. Agrawal May 11, 2010 Committee Members: Prof. Victor P. Nelson Prof. Fa F. Dai

Outline • • Study of Subthreshold Voltage Operation Dual Voltage Assignment Algorithm (MILP) Current Progress & Future Work Conclusion 2

Energy Constrained Systems • • Low activity rates Relaxed speed requirements Long battery lifetimes ( more than 1 year ) Energy harvesting from the environment Examples: Micro-sensor networks, Pacemakers, RFID tags, and Portable devices Energy Harvesting Tech. Power Density ( µW/cm 2 ) Vibration - electromagnetic Vibration - piezoelectric Vibration - electrostatic Thermoelectric ( 5°C difference) Solar - direct sunlight Solar - indoor 4. 0 500 3. 8 60 3700 3. 2 A. Wang, B. H. Calhoun, and A. P. Chandrakasan, Sub-Threshold Design for Ultra Low-Power Systems. Springer, 2006. 3

Subthreshold Operation (weak inversion) Eric A. Vittoz (1967) discovered that the transfer characteristics of MOS device were exponential across more than 5 decades of drain current. D Vds = Vdd G Vgs S Measurement of a MOS transistor at very low current (Vittoz’s notebook) E. A. Vittoz, “The Electronic Watch and Low-Power Circuits, ” IEEE Solid-State Circuits Newsletter, vol. 13, no. 3, pp. 7– 23, 2008. 4

Minimum Operating Voltage • Swanson and Meindl (1972) examined the voltage transfer characteristic (VTC) of an inverter: Minimum Voltage = 8 k. T/q or 200 m. V at 300 K (A ring oscillator worked at 100 m. V soon thereafter. ) • Ideal limit of the lowest possible supply voltage (2001) : Vdd = 2 k. T/q ≈ 57 m. V at 300 K R. M. Swanson and J. D. Meindl, “Ion-Implanted Complementary MOS Transistors in Low. Voltage Circuits, ” IEEE JSSC, vol. 7, no. 2, April 1972. A. Bryant, J. Brown, P. Cottrell, M. Ketchen, J. Ellis-Monaghan, E. Nowak, I. Div, and E. Junction, “Low-power CMOS at Vdd= 4 k. T/q, ” in Device Research Conference, 2001, pp. 22– 23. 5

VTC of Inverter in PTM 90 nm CMOS Functional Non-functional gain > 1 SPICE simulation ( Predictive Technology Model, PTM ) Vth_nmos = 0. 29 V, Vth_pmos = 0. 21 V Nominal VDD = 1. 2 V, Temp. = 300 K Inverter size: WP = 5. 5*L Wn = 2. 4*L L = 90 nm 6

180 m. V FFT Processor Dynamic Voltage Scaling (DVS) in subthreshold region according to operating scenarios ( 128 to 1024 FFT length and 8 or 16 bit precision) • • Tech. : Standard 018 µm 6 M CMOS (Vth = 450 m. V) Voltage scaling: 180 m. V to 900 m. V Operating Freq. : 164 Hz to 6 MHz Optimal operating point for 1024 and 16 b: Vdd, opt = 350 m. V Freq. = 9. 6 k. Hz Eopt = 155 n. J Above-threshold low power FFT processor consumes 3. 4 µJ in 0. 7 µm process with 1. 1 V A. Wang and A. Chandrakasan, “A 180 m. V FFT Processor Using Subthreshold Circuit Techniques, ” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2004, pp. 292– 529. 7

Minimum Energy Operating Point • Lowest energy per cycle Eopt = Minimum Etot = Edyn + Eleak Dynamic energy: Edyn Leakage energy : Eleak • Eopt normally occurs in subthreshold region if speed is not constrained • Speed critical operation: Vdd can be higher, even above-threshold 8

Vdd > Vth Dynamic Energy : • Edyn = α 0→ 1 CVdd 2 • Quadratic reduction with supply voltage Vdd • Activity factor α affects Edyn Leakage Energy : • Eleak = Pleaktd = Ileak. Vddtd • Ileak is composed of subthreshod leakage, gate leakage and pn junction reverse-bias current …. . • Normally smaller than dynamic energy 9

Vdd < Vth Dynamic Energy : • Edyn scaled down as Vdd 2 is comparable to Eleak Leakage Energy : • Assume Ileak ≈ Isub, off • td exponentially increases by scaling Vdd down • Eleak is independent of Vth A. Wang, B. H. Calhoun, and A. P. Chandrakasan, Sub-Threshold Design for Ultra Low. Power Systems. Springer, 2006. 10

Ileak and td Io : Drain current at Vgs=Vth S : Subthreshold swing η : Drain-induced barrier lowering ( DIBL ) VT : Thermal voltage (=k. T/q) Ileak = Isub, off = Isub (Vgs = 0) DIBL reduces Ileak with scaling Vdd K : Fitting parameter CL : Load capacitance Isub, on = Isub (Vgs = Vdd < Vth) 11

Normalized Ileak and td for INV (SPICE Simulation) Eleak is mainly dominated by td in subthreshold region. 12

Total Energy per Cycle ( Etot ) 8 -bit Ripple Carry Adder (PTM 90 nm CMOS) with α=0. 21 Vdd, opt = 0. 17 V Etot, min = 3. 29 f. J (1. 89 MHz) 13

Threshold Voltage Vs. Total Energy Lowering Vth does not change Eopt in the subthreshold region B. H. Calhoun, A. Wang, and A. Chandrakasan, “Modeling and Sizing for Minimum Energy Operation in Subthreshold Circuits, ” in IEEE Journal of Solid-State Circuits, Sept. 2005. 14

Energy Vs. Performance 14. 7 X 2. 7 X 59. 1 X 24. 5 X Delay and energy per cycle of 8 -bit ripple carry adder ( SPICE Simulation ) • Small increase of Etot in subthreshold region exponentially improves circuit speed 15

Outline • • Study of Subthreshold Voltage Operation Dual Voltage Assignment Algorithm (MILP) Current Progress & Future Work Conclusion 16

Motivation • Utilizing time slack for low power design is common in above-threshold, but not has been done in subthreshold operation • Small increase in Etot can significantly improves circuit speed • Two supply voltages are acceptable in today’s designs 17

Dual-Vdd Design • Use two supply voltages VDDH and VDDL • Apply VDDH to gates on critical paths to maintain performance (speed), while VDDL to gates on non-critical paths to reduce power • Use level converters at interfaces of VDDL cells feeding into VDDH cells 18

Driven Gates and Input Swing Level 19

Gate td and Pleak in Subthreshold Simulation data (PTM 90 nm CMOS) Two supply voltages VDDH = 250 m. V and VDDL = 200 m. V • Level converter has unacceptable delay overhead for subthreshold circuits: Gate Above-threshold (VDDH=1. 2 V, VDDL=0. 96 V) Sub-threshold (VDDH=250 m. V, VDDL=200 m. V) td (psec) Pleak (n. W) td (nsec) Pleak (p. W) INV Level converter (LC) 9. 54 68. 13 6. 87 31. 30 0. 83 254. 21 46. 2 214. 6 LC norm. to INV 7. 1 4. 6 306. 3 4. 7 20

Algorithm I : Eopt for Single Vdd • Characterize Standard cells for maximum delay, average leakage, and capacitances power using SPICE simulation over subthreshold region (100 m. V to 300 m. V, 10 m. V step, 21 points, PTM 90 nm CMOS) • Low to high signal activity from logic simulator • Critical delay Tc from STA (21 points) • Calculate Etot by the sum of energy for gates (21 points) • Find lowest Etot as Eopt 21

Algorithm I : Results 16 -bit ripple carry adder for single Vdd 22

Algorithm II : VDDL Assignment • VDDH and Tc are given as inputs from Algorithm I • Use repeatedly MILP to solve Etot and VDDL assignment to selected gates on the non-critical paths to achieve minimum energy for a pair of VDDH and VDDL ( Vmin=90 m. V ≤ VDDL < VDDH ) • Find Eopt and best VDDL Assignment corresponding to Eopt • Eliminate level converters in dual supply voltage operation by suitable constraints in MILP 23

MILP for VDDL Assignment For given speed requirement Tc ( VDDH ) Xi Integer variable : 0 for VDDH or 1 for VDDL Ti is the latest arrival time at a gate i output from PI events T. Raja, V. D. Agrawal, and M. L. Bushnell, “Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program, ” in Proceedings of 16 th International Conference on VLSI Design, Jan. 2003, pp. 527– 532. 24

Topological Constraints Xj Gate j Xi Gate i Xk Gate k HH: Xj = 0 and Xi = 0 → Xi – Xj = 0 LL: Xj = 1 and Xi = 1 → Xi – Xj = 0 HL: Xj = 0 and Xi = 1 → Xi – Xj = 1 LH: Xj = 1 and Xi = 0 → Xi – Xj = -1 25 Xi – X j ≥ 0

Example Result 16 -bit Ripple-Carry Adder (α=0. 21) in 90 nm Bulk CMOS Operation VDD (V) Energy/cycle (f. J) Clock rate Nominal 1. 2 252. 2 1. 35 GHz Minimum Energy Single VDD 0. 20 8. 71 2. 01 MHz Dual VDD ( energy opt. ) 0. 19, 0. 13 6. 82 1. 57 MHz Dual VDD ( perf. opt. ) 0. 26, 0. 18 8. 55 8. 12 MHz 26

Dual-Vdd Assignment Results # of paths 16 -bit ripple carry adder 22% reduction of Eopt 4 X 4 multiplier 3% reduction of Eopt tc 27 time

Outline • • Study of Subthreshold Voltage Operation Dual Voltage Assignment Algorithm (MILP) Current Progress & Future Work Conclusion 28

Current Progress • Validation of a dual-Vdd technique in bulk CMOS subthreshold circuits • A method for finding minimum energy operating point in single supply voltage • An MILP for dual supply voltages in subthreshold region • Level converter are avoided • A paper submitted to ICCAD 2010 29

Future Work • Modify topological constraints to allow suitable level converters or to use circuit techniques, then possibly more VDDL cells • Build MILP framework for minimum energy optimized circuit using dual-Vdd and highest speed • Minimum energy operating circuit immune to functional fails and process variations 30

Outline • • Study of Subthreshold Voltage Operation Dual Voltage Assignment Algorithm (MILP) Current Progress & Future Work Conclusion 31

Conclusion Dual-Vdd MILP framework for minimum energy operating circuit design is effective from minimum energy operating point to highest speed operation: v Ultra low power design without performance constraint v Minimum energy optimized design for given speed v Reduced energy optimization for highest speed 32

Thanks! 33