TRIO 2 Interconnect Modeling and Synthesis for Signal

  • Slides: 14
Download presentation
TRIO 2 Interconnect Modeling and Synthesis for Signal Integrity Project Leader: Prof. Lei He,

TRIO 2 Interconnect Modeling and Synthesis for Signal Integrity Project Leader: Prof. Lei He, LHE@EE. UCLA. EDU Authors: Jun Chen, Kevin Lepak, Min Xu UCLA Electrical Engineering Department Los Angeles, CA 90095 (Tools and references available at http: //eda. ee. ucla. edu) ASIC/SOC 2000, Lei He, http: //eda. ece. wisc. edu

Interconnect Design Closure Interconnect Synthesis + Global Routing Device locations and constraints: • Delay

Interconnect Design Closure Interconnect Synthesis + Global Routing Device locations and constraints: • Delay Topology Sizing • Power • Signal integrity • Skew. . . Spacing q Other critical optimizations: buffer insertion, shield insertion, simultaneous device and interconnect sizing … q Interconnect synthesis should be integrated with global routing for design closure 2

TRIO Package: Interconnect Synthesis under RC model q q Technology advances lead to the

TRIO Package: Interconnect Synthesis under RC model q q Technology advances lead to the need for interconnect-driven design Interconnect optimization techniques for performance u u u q Topology optimization Buffer (repeater) insertion Device sizing, wire sizing and spacing TRIO: Tree, Repeater, and Interconnect Optimization u u Reduce interconnect delay by up to 7 x Installed at Intel, IBM, HP, Fujitsu, and … TRIO = Performance Optimization under RC model 3

Is TRIO Sufficient for DSM Design? q Coupling capacitance becomes the dominant capacitance component

Is TRIO Sufficient for DSM Design? q Coupling capacitance becomes the dominant capacitance component q Inductive coupling gains more significance u u q Interconnect impedance is more than resistance • Z R +j L where 1/tr On-chip inductance should be considered • when L R due to smaller and quicker devices Coupling capacitance and inductance affect both delay and signal integrity u Signal integrity is one (or THE) upcoming barrier of design closure 4

Impact of Coupling Capacitance q Coupling capacitance introduces significant delay variations, especially for local

Impact of Coupling Capacitance q Coupling capacitance introduces significant delay variations, especially for local and intermediate interconnects 5

Resistance vs Inductance Length = 2000, Width = 0. 8 Thickness = 2. 0,

Resistance vs Inductance Length = 2000, Width = 0. 8 Thickness = 2. 0, Space = 0. 8 R and L for a single wire q Ls and Lx for two parallel wires Reactance due to inductance becomes comparable to resistance for 6 global interconnects

60 00 u Impact of Inductance 10 u Clk no shielding q 5 u

60 00 u Impact of Inductance 10 u Clk no shielding q 5 u Gnd 10 u Clk 5 u Gnd coplanar wave guide for inductance reduction Inductance introduces significant noise, especially for global interconnects 7

TRIO 2 q TRIO 2: integrated toolset for interconnect modeling, analysis and synthesis for

TRIO 2 q TRIO 2: integrated toolset for interconnect modeling, analysis and synthesis for signal integrity under RC and RLC models u u RC and RLC extraction • Table-based RC model (with process variations) [DAC’ 97, CICC’ 99] • Table-based R and L model [CICC’ 99, DATE’ 00, GVLSI’ 01] RC and RLC circuit model generation • 3 D full model based on PEEC and VPEC [submission] • 2 D cascade model and normalized model [DATE’ 00][GVLSI’ 01] Worst-case noise/delay model • Keff model, and Length scaled Keff model [ISPD’ 00, ICCAD’ 02] • Five-pole model, Decoupling model, WCN model, and t-line model [DAC’ 01, GVLSI’ 02, ASP-DAC’ 03] Interconnect synthesis • Shield insertion for buses and clocks [CICC’ 99] • Simultaneous shield insertion and net ordering [ISPD’ 00, DAC’ 01] • Power net and shielding co-design [ICCAD’ 01] • Clock synthesis (buffering and shielding to control noise and rising 8 time)

SINO: [ISPD’ 00, DAC’ 00, ICCAD’ 01] Simultaneous Shield Insertion and Net Ordering q

SINO: [ISPD’ 00, DAC’ 00, ICCAD’ 01] Simultaneous Shield Insertion and Net Ordering q q q Given: A set of signal nets, sensitivity, and noise bound Assume: Shields can be assigned to arbitrary tracks or uniform shielding with minimal perturbation Find: An SINO solution such that: u u u Capacitive noise free • No sensitive wires are adjacent • No neighboring wires switch simultaneously Inductive noise less than the given noise bound Minimal area 9

SINO Experiment Average number of shields Noise Bound q NO+SI SINO Sensitivity Rate =

SINO Experiment Average number of shields Noise Bound q NO+SI SINO Sensitivity Rate = 30% NO+SI SINO Sensitivity Rate = 60% 0. 15 V 7. 0 5. 4 (-23%) 10. 8 7. 85 (-30%) 0. 20 V 6. 15 5. 05( -14%) 10. 6 7. 45 ( -30%) 0. 25 V 6. 00 4. 2(-30%) 9. 75 7. 4(-33%) SINO achieves up to 33% shield reduction compared to best alternative (NO+SI) u 32 -bit signal bus, 2000 um long wire, in 70 nm technology 10

PWL Model for CPW q Piece-Wise Linear model computes the far end response for

PWL Model for CPW q Piece-Wise Linear model computes the far end response for a CPW with capacitive loading and ramp input u CPW: coplanar wave guide Transform CPW to transmission line without loading by moment matching Construct the waveform for step input of transmission line by 3 -piece linear approximation for each round trip of waveform Construct the waveform for ramp input by over 3 -piece approximation per round trip 11

PWL versus SPICE setting runtime model SPICE PWL work 3 work 4 1 88.

PWL versus SPICE setting runtime model SPICE PWL work 3 work 4 1 88. 1 0. 01 0. 18 2 148. 1 0. 01 0. 18 3 368. 23 0. 01 0. 12 4 23. 23 0. 01 0. 73 5 121. 39 0. 01 0. 2 6 344. 7 0. 01 0. 02 q PWL obtains highly accurate waveform in 1000 x less time u [4] and [5] (Meindl’ 00 and Eo’ 02) have much bigger errors 12

CPW Synthesis for Buffered Clock Tree a x 1 w 1 s 1 g

CPW Synthesis for Buffered Clock Tree a x 1 w 1 s 1 g 1 x 2 w 2 s 2 g 2 power 0 237 1. 5 4. 4 8. 2 149 1. 1 5. 0 10. 7 1769 ff 0. 3 288 1. 7 2. 9 3. 9 166 1. 2 2. 4 6. 3 1899 ff 1 500 4. 8 3. 2 2. 1 324 1. 5 2. 1 2952 ff q Tradeoff between area and power u u u Primarily decided by buffer size Min-power solution costs 3 x area than min-area solution, but 2 x less power Desired solution with α=0. 3 • Save 42% area with 4% more power compared to min-power solution • α – weighting factor to decide area/power tradeoff 13

Overall Design Closure for Signal Integrity TRIO 2 + Gsino + VPEC Layout TRIO

Overall Design Closure for Signal Integrity TRIO 2 + Gsino + VPEC Layout TRIO 2: R, L, C Extraction RC/RLC Circuit Generation PEEC VPEC Interconnect Synthesis Worst-Case Noise or Delay GSINO: GRouter Noise/Delay Violation Report q Iterative ECO flow u u q One-pass correctness by construction u q q Circuit modeling and analysis of critical nets (TRIO 2) Correction by net-based TRIO 2/Gsino Chip-level Gsino w/ embedded TRIO 2 and VPEC Gsino: global routing with simultaneous shielding and net ordering VPEC: vector potential equivalent circuit model, provably passive and 1000 x faster than PEEC 14