TriggerRegionUnit for PHOS Calorimeter H Muller R Pimenta

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Trigger-Region-Unit for PHOS Calorimeter H. Muller, R. Pimenta, D. Rohrich, B. Skaali, A. Oltean

Trigger-Region-Unit for PHOS Calorimeter H. Muller, R. Pimenta, D. Rohrich, B. Skaali, A. Oltean 1. PHOS in Alice Detector 2. Detector Components 3. Single Crystal Readout 4. Crystal Strip Units 5. FEE and TRU Packaging 8. Fast OR 6. Trigger Region FEE TRU Connectivity Trigger approach 7. 9. Front end Electronics (FEE) 10. Trigger Tasks General PHOS 11. Analog-Digital Conversion 12. Signal Routing Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 Implementation TRU 13. Serial ADC Interface 14. Oversampling 15. 480 Mb/s Deserializer 16. Level-0 Timing 17. Trigger Output at 40 MHz 18. TRU Card Status 1

PHOS in Alice Detector Electromagnetic Calorimeter ( photons and electrons) resolution goal is 3.

PHOS in Alice Detector Electromagnetic Calorimeter ( photons and electrons) resolution goal is 3. 5 % @ 1 Ge. V Alice Detector Single PHOS Module: 56 * 64 PWO crystals PHOS detector: 5 modules cover 5*20 degrees • • • Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 18. 000 PWO crystals 36. 000 readout channels Level-0, Level-1 Trigger 2

Detector Components one of 18. 000: Synthetically grown PWO crystal PHOS crystal cutout, polished

Detector Components one of 18. 000: Synthetically grown PWO crystal PHOS crystal cutout, polished CSP preamplifier APD (FET based) (Hamamatsu 5 mm 2) Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 3

Single Crystal Readout Photo of 1 assembled detector T-card Charge sensitive preamplifier (CSP) 1

Single Crystal Readout Photo of 1 assembled detector T-card Charge sensitive preamplifier (CSP) 1 Volt/pico-Coulomb (APD on backside) Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 4

Crystal Strip Units ( inside 1 module) L R FEE card Double Strip Unit

Crystal Strip Units ( inside 1 module) L R FEE card Double Strip Unit for 2*8 Crystals Alexandra Oltean for PHOS Trigger Project CERN, Left-Right orientation of 2 Double Strip Units = 1 FEE card (plugged below) September, 2005 5

FEE and TRU Packaging (fully embedded and water cooled) Technical: Conceptual: FEE cards 1

FEE and TRU Packaging (fully embedded and water cooled) Technical: Conceptual: FEE cards 1 TRU region 14 FEE cards TRU cards Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 6

Trigger Region 64 crystals ( 20 degree sector) 28 One TRU region PHOS module

Trigger Region 64 crystals ( 20 degree sector) 28 One TRU region PHOS module 3584 crystals 8 TRU domains 16 7 FEE cards 56 crystals TRU card 7 FEE cards 1 TRU = 448 (16 x 28) crystals 1 PHOS module (8 TRU) = 3584 (64 x 56) crystals Fast OR cables from FEE to TRU Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 7

Front End Electronics 32 channel Front-End Electronics card FEE card properties • 32 ch.

Front End Electronics 32 channel Front-End Electronics card FEE card properties • 32 ch. dual gain shapers • 32 APD bias regulators • 4 x 10 bit ADCs (Altro) • RMS noise 0. 4 ADC counts • 14 bit dyn range 5 Me. V– 80 Ge. V • Fast OR (2*2 ) for trigger • Board controller (PCM) • USB controller for tests • GTL+ readout bus (TPC) • Readout via RCU (TPC) • 5. 5 Watt, 349 * 210 mm 2 Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 8

Fast OR (FEE output) Copy CSP preamplifier signals into a fast shaper (100 ns)

Fast OR (FEE output) Copy CSP preamplifier signals into a fast shaper (100 ns) Analog output: charge sum of 2* 2 crystals • >95% of light in < 40 ns • Saturation at 32 Ge. V • Fast OR latency relative to preamplifier ~ 75 ns • L 0 trigger based on 100 ns charge signal Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 9

FEE TRU Connectivity Overview Crystals/Detector Analog/Digital Electronics Trigger Generation 112 analog inputs from 14

FEE TRU Connectivity Overview Crystals/Detector Analog/Digital Electronics Trigger Generation 112 analog inputs from 14 FEE cards Level-0 8 TRU Level-1 Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 10

Trigger Tasks (implemented in Xilinx FPGA) Level-0 Decision latency: 800 ns pre-trigger for Level-1

Trigger Tasks (implemented in Xilinx FPGA) Level-0 Decision latency: 800 ns pre-trigger for Level-1 use only low-bit threshold Level-1 Decision latency: 5 us high p. T photons Pb+Pb use only high-bit thresholds Alexandra Oltean for PHOS Trigger Project CERN, 1. – – – Level-0 ( FPGA Algorithm stage 1 ) sum up neighboring cells in space ( 4*4 cells) sum up analog Fast OR signal in time (100 ns) trigger if space-time sum is bigger than threshold detect signal peak in phase with 40 MHz output L 0 trigger as 40 MHz NRZ signal 2. Level-1 ( FPGA Algorithm stage 2) Only if level-0 has triggered: – determine space-time sum above 3 higher thresholds ( low, mid, high p. T) – send triggers to 3 outputs (low, mid, high) – store triggers in hit memory – trigger after max. 5 us September, 2005 11

Analog-Digital Conversion ( 112 analog inputs on TRU) Alexandra Oltean for PHOS Trigger Project

Analog-Digital Conversion ( 112 analog inputs on TRU) Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 12

Signal Routing (differential LVDS 480 Mb/s) One side of Allegro routing Xilinx Virtex-II Pro

Signal Routing (differential LVDS 480 Mb/s) One side of Allegro routing Xilinx Virtex-II Pro FPGA ( 1152 BGA) Difficulty: 112 differential signals of fixed polarization from ADC at controlled impedance ADCs, length adjusted routing Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 13

Serial ADC Interface (112 LVDS interfaces @ 480 Mb/s) • Original Problem: – Build

Serial ADC Interface (112 LVDS interfaces @ 480 Mb/s) • Original Problem: – Build 14 interfaces inside the FPGA (Xilinx Virtex-II Pro) for processing the 112 inputs (480 Mb/s) from the ADS devices • State of Art approach: – Standard solution (Xilinx AN - xapp 774) for connecting one ADS 527 X to XV 2 P 50 does not work in our case – This solution uses one Digital Clock Management (DCM) block per ADS interface – But: our design would need 14 x. DCMs for 14 different ADS interfaces and only 8 x. DCMs are available in the XV 2 P 50 • Proposed solution: – As a replacement for DCM use oversampling at 1. 44 GS/s to align the 112 DDR with 240 MHz high-speed clock – De. Serialize 112 DDR after oversampling and output the parallel data – Special attention given to constrain the interface design: maximum skew less than 300 ps, equal delays for all inputs, area groups inside the FPGA Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 14

Oversampling • Oversample and Shift DATAIN in 3 stages (1. 44 GS/s) • Align

Oversampling • Oversample and Shift DATAIN in 3 stages (1. 44 GS/s) • Align output to positive and negative edge of 240 MHz clock D D Q Clk 240_0 D Clk 240_60 D Clk 240_120 D Clk 240_180 D Clk 240_240 D Clk 240_300 ff_*_2 D Q Clk 240_0 D Q Clk 240_60 D Q Clk 240_0 Q D Clk 240_60 Q Q Q D Clk 240_0 Q Data. In_P Sync to clk 240_0 Q Sel_P[1: 0] D Clk 240_0 Q DMUX_P (running at 240 MHz) ff_*_1 DATAIN Q Q DMUX_N • DATAIN Serial DDR from ADS 5270 Data. In_N Sync to clk 240_0 Q Sel_N[1: 0] 1 st stage Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 2 nd stage 3 rd stage 15

De. Serializer ( LVDS input @ 480 Mb/s to 12 bit register ) D

De. Serializer ( LVDS input @ 480 Mb/s to 12 bit register ) D Q D Flip-Flop Cascade Q Q Q D Clk 240_0 Q 5 Q 4 Q 3 Q 2 Ena. Reg. Clk 0 E Q 1 Q 0 Data. In_N D D Q Q Q Q Flip-Flop Cascade Q 5 Q 4 Data Multiplexer Deserializer • 2 FF cascades for even and odd bits • 2 parallel registers , clocked on the positive and negative edge of 240 Mhz clock • Multiplexer used to align (swap if necessary) odd and even bits in the final 12 -bit register Data. In_P Data[0: 11] Input data • Data. In_P and Data. In_N aligned in the oversampling module Dat. Out[11: 0] Q 3 Q 2 Clk 240_180 Ena. Reg. Clk 180 Output data • 12 -bit parallel data Data. Out[11: 0] Alexandra Oltean for PHOS Trigger Project CERN, E Q 1 Q 0 Ena. Mux September, 2005 16

Level-0 Timing Level-0 FPGA Process: 112 @ 40 MHz synchronous pipelined space-time summing and

Level-0 Timing Level-0 FPGA Process: 112 @ 40 MHz synchronous pipelined space-time summing and threshold compare Available time in the FPGA: maximum 440 ns Analog 40 MHz Interaction time t=0 TOF shower APD ( 20 ns) 40 MHz NRZ serial Trigger Digital ( 20 ns) analog Sum (10 ns) (80 ns) 12 bit ADC (28 ns) Over De. Ser Samp (25 ns) (15 ns) 4*4 space Sum (25 ns) 4 -deep time summing 25 ns pipeline 160 ns peak compare thresh. FPGA ~ 200 ns ~ 350 ns Central Trigger NRZ ~ 40 m = 200 ns ~ 400 ns 600 ns out of FPGA fixed delay Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 max. 800 ns (L 0) 17

Trigger Output @ 40 MHz ( NRZ encoded) Warm zone isolator TRU output TRU

Trigger Output @ 40 MHz ( NRZ encoded) Warm zone isolator TRU output TRU 2 LHC CLOCK 40 MHz L 0_yes from all 91 TRU 3 D kernel areas TRU 4 TRU 8 ~ 40 m ( 200 ns) OR ALICE Central Trigger typical trigger out Yes. No. No No. Yes. No Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 18

TRU Card Status ( Layout finalized, Prototypes Nov. 05 ) 2*4 serial out Quad

TRU Card Status ( Layout finalized, Prototypes Nov. 05 ) 2*4 serial out Quad Rocket I/O option RG 45 LV regulator Reconfiguration logic FPGA • 11 layer board • 6 signal layers 14 octal ADC both sides USB Cooling pipe RG 45 Power connector V 0 - L 0 out input 3* L 1 out GTL-bus ( address 0) 14 * analog OR input connectors Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 19

Conclusions • PHOS modules contain 3584 crystals with preamplifiers • FEE and TRU cards

Conclusions • PHOS modules contain 3584 crystals with preamplifiers • FEE and TRU cards are packaged inside closed PHOS modules • TRU card – covers 1/8 of one PHOS module (448 crystals) – 112 analog Fast OR inputs from surrounding FEE cards – central element is Xilinx Virtex-II Pro FPGA with 112 serial ADC inputs – Level-0 is low-threshold algorithm pre-trigger for Level-1 – Level-1 is high-threshold algorithm with 3 trigger outputs – Oversampling approach for 480 Mb/s LVDS input deserializer • First TRU prototype expected November 05 Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 20

Acknowledgements To Gerd Troeger (Kirchhoff Institut fuer Physik Heidelberg) for the helpful discussions and

Acknowledgements To Gerd Troeger (Kirchhoff Institut fuer Physik Heidelberg) for the helpful discussions and guidelines during the development of the trigger algorithm Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 21

Trigger-Region-Unit for PHOS Calorimeter H. Muller, A. Oltean, R. Pimenta, D. Rohrich, B. Skaali

Trigger-Region-Unit for PHOS Calorimeter H. Muller, A. Oltean, R. Pimenta, D. Rohrich, B. Skaali Thank you! Alexandra Oltean for PHOS Trigger Project CERN, September, 2005 22