Trigger Data Serializer chip design and test for

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Trigger Data Serializer chip design and test for the ATLAS forward muon upgrade Reid

Trigger Data Serializer chip design and test for the ATLAS forward muon upgrade Reid Pinkham On behalf of the ATLAS Muon Collaboration University of Michigan APS April Meeting April 18, 2016 1

Background: new Small Wheel X ~ 10 m u Replace the present ATLAS Small

Background: new Small Wheel X ~ 10 m u Replace the present ATLAS Small Wheel with a new Small Wheel for the Phase-I upgrade § Current system has many “fake” LV 1 triggers and not designed for the increased hit rate at high luminosities § Replace MDT+TGC with MM+s. TGC that will work at 15 k. Hz/cm 2 § Provide a segment measurement at n. SW with an angular resolution of 1 mrad § Use measurements from both detectors as part of LV 1 trigger new Small Wheel (n. SW) 2

Background: Detector Technology for the new Small Wheel u New detector, new technology! §

Background: Detector Technology for the new Small Wheel u New detector, new technology! § Micromesh Gaseous Structure Detector, Micromegas (MM) § Small-strip Thin Gap Chamber (s. TGC) § 4 s. TGC + 4 MM + 4 s. TGC MM 16 layers in total Readout channels: • MM: ~ 2. 1 M • s. TGC: 280 k (strip) + 46 k (pads) + 28 k (wires) = 354 k ~ 40 cm s. TGC (~8 cm) 3

Background: Data Flow and the TDS’ Function Hit to Sector Logic: 1μs Trigger Path

Background: Data Flow and the TDS’ Function Hit to Sector Logic: 1μs Trigger Path Readout Path 4

Application Specific Integrated Circuit (ASIC) Two operation modes: § Pad-TDS: send each pad’s firing

Application Specific Integrated Circuit (ASIC) Two operation modes: § Pad-TDS: send each pad’s firing status to pad trigger § Strip-TDS: prepare strip trigger data, perform pad-strip matching and serialize the charge for matched strips Output data rate: 4. 8 Gbps Low and fixed latency needed (40 ns for pad. TDS and 75 ns for strip-TDS) Radiation tolerant 5. 2 mm § § 21 mm TDS Design: Requirements and Packaging § § § Silicon Die Strip-TDS Block Diagram ASIC Package 5

TDS Testing: Test Setup u Dedicated test board was required • 132 differential inputs

TDS Testing: Test Setup u Dedicated test board was required • 132 differential inputs from Artix-7 FPGA to TDS • 2 epll generated 160 MHz clock sent to FPGA: emulate TDS-VMM communication • 2 pairs of trigger lines: emulate TDS-Pad Trigger link • TDS Serializer output sent to Artix-7 Receiver u Clocks • Synchronized clock for TDS and data generator in FPGA: know when and what to look for Artix-7 Packaged TDS on Test Board 6

TDS Testing: Signal Quality Eye Diagram Measurements TDS v 1 TXN TXP 100 W

TDS Testing: Signal Quality Eye Diagram Measurements TDS v 1 TXN TXP 100 W High input resistance Probe Bit Error Rate (BER): PRBS TXPTXN Tektronix DSA (12. 5 GHz BW) 4. 8 Gbps q Total jitter @ (BER 10 -12): 33. 2 ps q Random jitter (RMS): 2. 3 ps q Deterministic jitter: 4. 6 ps q Periodic jitter: 4. 6 ps q Duty cycle distortion: 0. 02 ps 4. 8 Gbps Pseudorandom Binary Sequence (PRBS) sent from TDS and checked on FPGA q Use a 4 m Twinax cable as in detector q BER less than 10 -15 q c TDS has great signal quality and integrity 7

TDS Testing: Packaged Chip Functional Test, Strip Mode: Simulate VMM pulses to channels §

TDS Testing: Packaged Chip Functional Test, Strip Mode: Simulate VMM pulses to channels § VMM charge input to selected channels § Charge = Channel Number § Returned observed charge § Correct charge and Bunch Crossing Identification (BCID) on all channels Packet 5 [23: 0] Packet 4 [47: 24] Packet 3 [63: 48] Packet 2 [95: 63] Packet 1 [119: 96] VMM 6 -bit Charge Output for Trigger Emulated VMM-input sent to TDS Data captured by Logic Analyzer (Xilinx ILA) 8

TDS Testing: Packaged Chip Functional Test, PAD Mode Send emulated timing pulses to all

TDS Testing: Packaged Chip Functional Test, PAD Mode Send emulated timing pulses to all 96 pad channels every 46 Bunch Crossings (BCs) Results: observed hits from all pad channels in the decoded Serializer output data 160 MHz Clock Emulated Pad Timing pulse An example event showing 16 pad channels aligned to the same BC Decoded Pad Hits from a group of Channel # 46 BC Decoded BCID Data captured by Logic Analyzer (Xilinx ILA) 9

TDS Design: Version II TDSVI logic (strip+pad) 2. 3 mm x 2. 3 mm

TDS Design: Version II TDSVI logic (strip+pad) 2. 3 mm x 2. 3 mm 5. 2 mm TDSVII logic (strip + pad) 2. 9 mm x 3. 4 mm 5. 2 mm New Features § Channel-by-channel enable/disable § TMR for all configuration bits and clock trees § New Pin mapping § Same die size (5. 2 mm per side) Design submitted in February, Sent to Fabrication in April 10

Summary and Remarks u The Muon system’s Small Wheel is being replaced as part

Summary and Remarks u The Muon system’s Small Wheel is being replaced as part of the phase-1 upgrade § This is needed to improve the LV 1 muon trigger and maintain precision tracking at high luminosity u The Triger Data Serializer has two functional modes u Serialize pad hit information u Serialize charge information from the s. TGCs u Systematic functional tests of the TDSv 1 carried out, no issues found u Output signal has very good quality and integrity u All channels function expected in PAD and Strip mode u TDSv 2 has been designed and submitted for fabrication 11

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Background: Role of Small Wheel in the ATLAS Detector u ATLAS has the world’s

Background: Role of Small Wheel in the ATLAS Detector u ATLAS has the world’s largest muon spectrometer and can measure muon p. T with a resolution of 10% at 1 Te. V § Precision tracking chambers: MDT + CSC in SW § Trigger chambers: TGC in the endcap 13

Background: Motivation for Upgrade u Current Muon Spectrometer uses only the Big Wheel for

Background: Motivation for Upgrade u Current Muon Spectrometer uses only the Big Wheel for LV 1 Trigger u Problems with the current spectrometer in the endcap: § LV 1 muon triggers rely on the BW TGC ~80% of muons found at LV 1 are fake § Large hit rate expected at the HL-LHC low MDT hit and track segment efficiencies Extrapolated hit rate based on current CSC data “Fake” Muon Extrapolated hit rate based on current MDT data MDT limitation 14

TDS Testing: Packaged Chip Power Consumption LDO 1. 5 V (Analog) u Measurement Approach:

TDS Testing: Packaged Chip Power Consumption LDO 1. 5 V (Analog) u Measurement Approach: Current monitoring for 1. 5 V power rails and 2. 5 V DVDD rail using current sensing resistors LDO 1. 5 V (Digital) Current sensing resistors (0. 075 W) u Results: 1. 5 V Analog* 1. 5 V Digital** 2. 5 V DVDD*** Total (W) Static (Power-on w. 40 MHz clk) 0. 38 0. 07 0. 75 Strip-Mode (Trig. via Config. port) 0. 31 0. 45 0. 03 0. 79 Strip-Mode (Trig. via Pad Trig. Interface) 0. 31 0. 43 0. 01 0. 75 Pad-Mode 0. 3 0. 43 0. 02 0. 75 Power for analog (pll) logic IO Power for digital logic IO *** Power for configuration logic • Good agreement with simulation: digital (~ 0. 3 W)+ SER 0. 33 W+ IO (0. 15 W) = 0. 75 W * ** 15

BACKUP TDS Testing: Wire-Bond Board Wire-bonded Chips allowed for quick testing before packaged chips

BACKUP TDS Testing: Wire-Bond Board Wire-bonded Chips allowed for quick testing before packaged chips arrived 1 in 4 wire-bonded chips succeeded Small pitch and dual-row I/O pads were challenging to work with Could configure chip successfully Only a handful of channels connected Available channels worked! TDS die wire bonded to PCB 16

TDS Testing: Packaged Chip Functional Test, Strip Mode: Simulate VMM pulses to channels §

TDS Testing: Packaged Chip Functional Test, Strip Mode: Simulate VMM pulses to channels § VMM charge input to selected channels § Charge = Channel + 2 § Returned observed charge § Correct charge and BCID on all channels Packet 5 [23: 0] Packet 4 [47: 24] CH 53 CH 54 CH 55 CH 56 Packet 3 [63: 48] CH 49 CH 50 CH 51 CH 52 Packet 2 [95: 63] CH 45 CH 46 CH 47 CH 48 Packet 1 [119: 96] VMM 6 -bit Charge Output for Trigger Emulated VMM-input sent to TDS CH 42 CH 43 CH 44 Data captured by Logic Analyzer (Xilinx ILA) 17

TDS + 4 m twinwax Repeater* Board #1 Artix-7 TDS 4. 8 Gbps Board

TDS + 4 m twinwax Repeater* Board #1 Artix-7 TDS 4. 8 Gbps Board #2 Artix-7 TDS 4 -m Twinax Cable ( • 8 F 36) Error free for both setup after 4 x 1015 bits transmitted (10+ days): BER=7 x 10 -16 @ 95%CL