Trends and Section Wrap up Accelerated SimulationEmulation HWSW

Trends and Section Wrap up ▪ Accelerated Simulation/Emulation ▪ HW+SW Co- Verification with System Verilog 9/13/2021 1

Hardware-Accelerated Simulation ▪ Simulation performance is improved by moving the time-consuming part of the design to hardware. Verification with System Verilog 9/13/2021 2

Hardware-Accelerated Simulation ▪ Challenges ▪ Improves speed but degrades on HW-SW communication ▪ Abstracting HW-SW communication at transaction level rather than cycle level desired for better speeds ▪ HW Emulation ▪ Full mapping of HW into an emulator (array of FPGAs) ▪ More like a real target system. Speed up possible up to 1000 X simulation ▪ Debug is a challenge with limited visibility ▪ Usually used for HW+SW co-verification Verification with System Verilog 9/13/2021 3

HW/SW Co-Verification ▪ SOC designs involve both HW and SW development ▪ HW and SW components are verified separately but needs to work together in real product ▪ Co-Verification will help projects to complete in short time and with higher confidence on both HW and SW quality 9/13/2021 Verification with System Verilog 4

Section Summary ▪ What We learned ? ▪ What/Why - Verification ? ▪ Different methods – Simulation/Formal/Assertion ▪ Directed vs Random Testing and Coverage ▪ Other Trends – Emulation and HW+SW ▪ Please go through the next exercise to apply these concepts on a case study 9/13/2021 5