Transistor Odds and Ends PHY 201 Blum 1

Transistor Odds and Ends PHY 201 (Blum) 1

RTL NOR PHY 201 (Blum) 2

NOT from NOR PHY 201 (Blum) 3

OR from NOR PHY 201 (Blum) 4

AND from NOR PHY 201 (Blum) 5

Combinatorial Logic • From the NOR, we have made ANDs, ORs and NOTs. And from these we can build an expression for any truth table. • Any logic that can be written in truth table form (with only reference to the current inputs) is said to be combinatorial. • Recall we can build any combinatorial circuit using ANDs, ORs and NOTs. PHY 201 (Blum) 6

Example: Majority Rules A 0 0 0 B 0 0 1 C 0 1 0 Majority 0 0 1 1 1 0 1 1 1 PHY 201 (Blum) If two or more of the three inputs are high, then the output is high. 7

Row Expressions A 0 0 0 B 0 0 1 C 0 1 0 Row expressions A’B’C’ A’B’C A’BC’ 0 1 1 1 0 1 A’BC AB’C’ AB’C ABC’ ABC PHY 201 (Blum) The highlighted rows correspond to the high outputs. 8

Sum of products • Each row is represented by the ANDing of inputs and/or inverses of inputs. – E. g. A’BC – Recall that ANDing is like Boolean multiplication • The overall expression for the truth table is then obtained by ORing the expressions for the individual rows. – Recall that ORing is like Boolean addition – E. g. A’BC + AB’C + ABC’ + ABC • This type of expression is known as a sum of products expression. PHY 201 (Blum) 9

Majority rules • A´BC + AB´C + ABC´ + ABC NOTs OR PHY 201 (Blum) ANDs 10

Other Logic Families • As one has an increasing number of logic gates one has to be concerned with their power performance and stability. • The logic gates can be made out of various combinations of resistors, diodes, and transistors. They differ in power and stability. • Let us examine an inverter from the TTL (transistor-transistor logic) family. PHY 201 (Blum) 11

TTL Inverter PHY 201 (Blum) 12

TTL Inverter PHY 201 (Blum) 13

On-Off • Recall that a transistor can be thought of a switch. – When the switch is off, the transistor has very high resistance. – When the switch is on, the transistor has relatively low resistance. • It “transfers resistances. ” PHY 201 (Blum) 14

Transistor etymology PHY 201 (Blum) 15

Totem Pole • The right-hand side of the TTL inverter is an arrangement of transistors known as a totem pole. • The transistors are arranged to that one is on and one is off. • The inverter output is just above the lower transistor in the totem pole. – If the lower transistor is on, there is little voltage drop across the lower transistor and so the output voltage is close to 0 (ground). PHY 201 (Blum) 16

Totem Pole (Cont. ) – If the lower transistor is off, then there is a large voltage drop across the lower transistor and so the output voltage is high. • One is almost directly connected to the high or the ground giving this arrangement good power/stability characteristics. PHY 201 (Blum) 17

Similar arrangement/Opposite idea • In the totem pole arrangement, one guarantees that one of the two transistors in on and the other is off – giving a low-resistance connection to high or low as the case may be. • If we arrange for a third possibility that both transistors are off, then there is a high resistance between the output and both the high and the low. • This high-resistance or high-impedance state is neither high nor low, but effectively disconnected. PHY 201 (Blum) 18

Poor Man’s Tri. State PHY 201 (Blum) 19

Poor Man’s Tri. State PHY 201 (Blum) 20

Poor Man’s Tri. State PHY 201 (Blum) 21

Poor Man’s Tri. State PHY 201 (Blum) 22

Same idea as the tri-state buffer • This circuit has the essential ingredients to make a tri-state buffer. • Recall that tri-state buffers are used in conjunction with buses. • When one has several devices that could place their information on the bus (“drive the bus”) only one of them should. – If two devices attempt to drive the bus to opposite voltage levels, there will be a short. PHY 201 (Blum) 23

Three State Logic A E Output 0 0 0 1 Z (High impedance) 0 1 0 Z (High impedance) 1 1 1 PHY 201 (Blum) 24

Tri-state buffer PHY 201 (Blum) Compare the Electronics Workbench tri-state buffer to the previous circuit made of transistors and logic gates. 25

In the high impedance state PHY 201 (Blum) 26

In the high impedance state PHY 201 (Blum) 27

In the “enabled” state PHY 201 (Blum) 28

In the “enabled” state PHY 201 (Blum) 29

Sequential Logic • Whereas combinatorial logic depends only on the current inputs, sequential logic can also depend on the previous “state” of the system. • Circuitry designed to hold a high or low state is known as a flip-flop. • A flip-flop is the smallest unit of RAM – random access memory. • Recall there are two basic categories of RAM: dynamic RAM (DRAM) and static RAM (SRAM). PHY 201 (Blum) 30

Flip Flops • Flip-flops serve as the elementary units for memory in digital systems. Two features are needed: • 1. The circuit must be able to “hold” either state (a high or low output) and not simply reflect the input at any given time. • 2. But in some circumstances, we must be able to change (to “set” and “reset”) the values. PHY 201 (Blum) 31

Remembrance of states past • The way in which the previous state information is held is different for different types of memory • In DRAM (dynamic random access memory), the state (1 or 0) is held by a charge (or lack thereof) remaining on a capacitor – Charges tend to leak off of capacitors, which is why DRAM must be periodically refreshed PHY 201 (Blum) 32

Simple DRAM (Reset) PHY 201 (Blum) 33

Simple DRAM (Set) PHY 201 (Blum) 34

Simple DRAM (Hold) PHY 201 (Blum) 35

Simple DRAM (Hold) PHY 201 (Blum) 36

Simple DRAM (Reset) PHY 201 (Blum) 37

Simple DRAM (Hold) PHY 201 (Blum) 38

Simple DRAM (Hold) PHY 201 (Blum) 39

SRAM • In SRAM (static random access memory) the history dependence is achieved via a feedback mechanism. • Feedback: the return of part of the output to the input of a mechanism, process or system (source: Random House Dictionary). • SRAM does not need refreshing, making it faster, but it is more expensive; typically it is reserved for caching and other high-speed situations. PHY 201 (Blum) 40

RS Flip Flop PHY 201 (Blum) feedback 41

Electronics Workbench info on RS flip-flop PHY 201 (Blum) 42

RS Flip Flop • The Q output is inverted and fed back in as an input • Similarly the Q’ output is inverted and fed back in as an input • As suggested by the names Q and Q’, these outputs are supposed to be inverses of one another PHY 201 (Blum) 43

The hold operation • The S=0, R=0 is the hold “state”, the flip flop keeps its previous outputs • Imagine Q=1 and Q’=0, – Then Not Q’ (which is 1) is ORed with S giving a 1 for the Q output – Then Not Q (which is 0) is ORed with R giving a 0 for the Q’ output – The output is the same as the input (no change) PHY 201 (Blum) 44

The hold operation • The S=0, R=0 is the hold “state”, the flip flop keeps its previous outputs • Imagine Q=0 and Q’=1, – Then Not Q’ (which is 0) is ORed with S giving a 0 for the Q output – Then Not Q (which is 1) is ORed with R giving a 1 for the Q’ output – The output is the same as the input (no change) PHY 201 (Blum) 45

The set operation • The S=1, R=0 is the set “state”, the flip flop force Q=1 • Imagine Q=0 and Q’=1, – Then Not Q’ (which is 0) is ORed with S giving a 1 for the Q output – Then Not Q (which is now 0) is ORed with R giving a 0 for the Q’ output – The Q output is forced to be (set to) 1 PHY 201 (Blum) 46

The set operation • The S=1, R=0 is the set “state”, the flip flop forces Q=1 • Imagine Q=1 and Q’=0, – Then Not Q’ (which is 1) is ORed with S giving a 1 for the Q output – Then Not Q (which is 0) is ORed with R giving a 0 for the Q’ output – The Q output is forced to be (set to) 1 PHY 201 (Blum) 47

The reset operation • The S=0, R=1 is the reset “state”, the flip flop forces Q=0 • Imagine Q=0 and Q’=1, – Then Not Q’ (which is 0) is ORed with S giving a 0 for the Q output – Then Not Q (which is 1) is ORed with R giving a 1 for the Q’ output – The Q output is forced to be (reset to) 0 PHY 201 (Blum) 48

The reset operation • The S=0, R=1 is the reset “state”, the flip flop forces Q=0 • Imagine Q=1 and Q’=0, – Then Not Q’ (which is 1) is ORed with S giving a 1 for the Q output – Then Not Q (which is now 0) is ORed with R giving a 1 for the Q’ output – Then Not Q’ (which is now 0) is ORed with S giving a 0 for the Q output – The Q output is forced to be (reset to) 0 PHY 201 (Blum) 49

The undesired operation • The S=1, R=1 is the undesired “state” • Imagine Q=0 and Q’=1, – Then Not Q’ (which is 0) is ORed with S giving a 1 for the Q output – Then Not Q (which is now 0) is ORed with R giving a 1 for the Q’ output – And so on – The Q and Q’ outputs are equal, which is undesired PHY 201 (Blum) 50

Level clocking PHY 201 (Blum) 51

Level clocking • Adding an additional layer of AND gates and an extra input makes the flip flop “clocked” • What used to be the S input is now S ANDed with CLK, so the set action is now obtained only when S=1 AND CLK=1 • This helps control when the setting occurs and keeps this action in sync with other operations occurring in the circuit PHY 201 (Blum) 52

Edge triggering Two RS flip-flops in a Master-slave arrangement. PHY 201 (Blum) 53

Edge Triggering • Feeding the outputs of one clocked RS flip flop into a second flip flop in which the clock input is inverted results in an edgetriggered flip flop • The first flip flop acts as a level clocked flip flop, that is, setting and resetting occur only when the CLK input is 1 PHY 201 (Blum) 54

Edge triggering (cont. ) • During this period, the second RS flip flop is getting the inverse of the CLK and so is in the no change state • When the CLK goes to 0, the first flip flop goes into its no change state and the second flip flop can be set or reset PHY 201 (Blum) 55

Edge triggering • What is setting or resetting the second flip flop are the outputs of the first flip flop and they are held fixed • This way the inputs to the second flip flop can not vary through the course of the clock’s cycle • Whatever they were when the clock switched is what is important PHY 201 (Blum) 56

SRAM Pros • Speed – SRAM is faster than DRAM, because DRAM requires refreshing which takes time • Simplicity – SRAM is simpler to use than DRAM, again because DRAM requires refreshing PHY 201 (Blum) 57

SRAM Cons • Size – SRAM is a more complicated circuit, it involves more transistors than DRAM, and hence it is larger • Cost – Again SRAM is more transistors and so it costs more • Power – Since SRAM involves a constant current, it uses more power than DRAM • Heat – Again since SRAM involves a constant current, it produces more heat PHY 201 (Blum) 58