Topics Wire and via structures n Wire parasitics
- Slides: 16
Topics Wire and via structures. n Wire parasitics. n FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Wires and vias metal 3 metal 2 vias metal 1 poly n+ p-tub FPGA-Based System Design: Chapter 2 poly n+ Copyright 2004 Prentice Hall PTR
Metal migration Current-carrying capacity of metal wire depends on cross-section. Height is fixed, so width determines current limit. n Metal migration: when current is too high, electron flow pushes around metal grains. Higher resistance increases metal migration, leading to destruction of wire. n FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Metal migration problems and solutions Marginal wires will fail after a small operating period—infant mortality. n Normal wires must be sized to accomodate maximum current flow: n Imax = 1. 5 m. A/ m of metal width. n Mainly applies to VDD/VSS lines. FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Diffusion wire capacitance n Capacitances formed by p-n junctions: sidewall capacitances depletion region n+ (ND) substrate (NA) FPGA-Based System Design: Chapter 2 bottomwall capacitance Copyright 2004 Prentice Hall PTR
Depletion region capacitance n Zero-bias depletion capacitance: – Cj 0 = si/xd. n Depletion region width: – xd 0 = sqrt[(1/NA + 1/ND)2 si. Vbi/q]. n Junction capacitance is function of voltage across junction: – Cj(Vr) = Cj 0/sqrt(1 + Vr/Vbi) FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Poly/metal wire capacitance n Two components: – parallel plate; – fringe plate FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Metal coupling capacitances n Can couple to adjacent wires on same layer, wires on above/below layers: metal 2 metal 1 FPGA-Based System Design: Chapter 2 metal 1 Copyright 2004 Prentice Hall PTR
Wire resistance n Resistance of any size square is constant: FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Metal mean-time-to-failure MTF for metal wires = time required for 50% of wires to fail. n Depends on current density: n – proportional to j-n e Q/k. T – j is current density – n is constant between 1 and 3 – Q is diffusion activation energy FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Skin effect At low frequencies, most of copper conductor’s cross section carries current. n As frequency increases, current moves to skin of conductor. n – Back EMF induces counter-current in body of conductor. n Skin effect most important at gigahertz frequencies. FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Skin effect, cont’d n Isolated conductor: Low frequency n Conductor and ground: Low frequency High frequency FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Skin depth n Skin depth is depth at which conductor’s current is reduced to 1/3 = 37% of surface value: – d = 1/sqrt(p f s) – f = signal frequency – = magnetic permeability – s = wire conductivity FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Effect on resistance n Low frequency resistance of wire: – Rdc = 1/ s wt n High frequency resistance with skin effect: – Rhf = 1/2 s d (w + t) n Resistance per unit length: – Rac = sqrt(Rdc 2 + k Rhf 2) n Typically k = 1. 2. FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Wire capacitance and resistance Metal 3 Capacitance to ground (a. F/ m) 18 Coupling capacitance (a. F/ m) 9 Resistance/ length (W/ m) 0. 2 Metal 2 47 24 0. 3 Metal 1 76 36 0. 3 FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
Gate delay vs. wire delay Minimum-size inverter delay: 2. 9 ps n Length of wire with equal delay---assume wire with capacitance equal to inverter input capacitance = 0. 12 f. F. n – Metal 3 length is 6. 7 m. – About 75 times width of minimum-size transistor. FPGA-Based System Design: Chapter 2 Copyright 2004 Prentice Hall PTR
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