Topics Pseudon MOS gates n DCVS gates n

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Topics Pseudo-n. MOS gates. n DCVS gates. n Domino gates. n Modern VLSI Design

Topics Pseudo-n. MOS gates. n DCVS gates. n Domino gates. n Modern VLSI Design 3 e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR

Pseudo-n. MOS n Uses a p-type as a resistive pullup, n-type network for pulldowns.

Pseudo-n. MOS n Uses a p-type as a resistive pullup, n-type network for pulldowns. Always on. Modern VLSI Design 3 e: Chapter 3 a b out 0 0 1 0 1 0 0 1 1 0 Copyright 1998, 2002 Prentice Hall PTR

Characteristics Consumes static power. n Has much smaller pullup network than static gate. n

Characteristics Consumes static power. n Has much smaller pullup network than static gate. n Pulldown time is longer because pullup is fighting. n Modern VLSI Design 3 e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR

Output voltages Logic 1 output is always at VDD. n Logic 0 output is

Output voltages Logic 1 output is always at VDD. n Logic 0 output is above Vss. n VOL = 0. 25 (VDD - VSS) is one plausible choice. n Modern VLSI Design 3 e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR

Producing output voltages For logic 0 output, pullup and pulldown form a voltage divider.

Producing output voltages For logic 0 output, pullup and pulldown form a voltage divider. n Must choose n, p transistor sizes to create effective resistances of the required ratio. n Effective resistance of pulldown network must be computed in worst case—series ntypes means larger transistors. n Modern VLSI Design 3 e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR

Transistor ratio calculation n In steady state logic 0 output: – pullup is in

Transistor ratio calculation n In steady state logic 0 output: – pullup is in linear region, Vds = Vout - (VDD VSS) ; – pulldown is in saturation. n Pullup and pulldown have same current flowing through them. Modern VLSI Design 3 e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR

Transistor ratio, cont’d. n Equate two currents with pull-down transistor in saturation and pull-up

Transistor ratio, cont’d. n Equate two currents with pull-down transistor in saturation and pull-up in linear region: – Idp = Idd. n Using 0. 5 mm parameters, 3. 3 V power supply: – Wp/Lp / Wn/Ln = 3. 9. Modern VLSI Design 3 e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR

DCVS logic n n DCVSL = differential cascode voltage logic. Static logic—consumes no dynamic

DCVS logic n n DCVSL = differential cascode voltage logic. Static logic—consumes no dynamic or static power. Uses latch to compute output quickly. Requires true/complement inputs, produces true/complement outputs. n The cascode (sometimes verbified to cascoding) is a universal technique for improving analog circuit performance, applicable to both vacuum tubes and transistors. The word was first used in an article by F. V. Hunt and R. W. Hickman in 1939, in a discussion for application in low-voltage stabilizers. They proposed a cascade of two triodes (first one with common cathode, the second one with common grid) as a replacement of a pentode. n http: //en. wikipedia. org/wiki/Cascode Modern VLSI Design 3 e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR

DCVS structure Modern VLSI Design 3 e: Chapter 3 Copyright 1998, 2002 Prentice Hall

DCVS structure Modern VLSI Design 3 e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR

DCVS operation Exactly one of true/complement pulldown networks will complete a path to the

DCVS operation Exactly one of true/complement pulldown networks will complete a path to the power supply. n Pulldown network will lower output voltage, turning on other p-type, which also turns off p-type for node which is going down. n Modern VLSI Design 3 e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR

DCVS example Modern VLSI Design 3 e: Chapter 3 Copyright 1998, 2002 Prentice Hall

DCVS example Modern VLSI Design 3 e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR

Precharged logic uses stored charge to help evaluation. n Precharge node, selectively discharge it.

Precharged logic uses stored charge to help evaluation. n Precharge node, selectively discharge it. n Take advantage of higher speed of n-types. n Requires multiple phases for evaluation. n Modern VLSI Design 3 e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR

Domino logic n Uses precharge clock to compute output in two phases: – precharge;

Domino logic n Uses precharge clock to compute output in two phases: – precharge; – evaluate. n Is not a complete logic family—cannot invert. Modern VLSI Design 3 e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR

Domino gate structure Domino OR gate Modern VLSI Design 3 e: Chapter 3 Copyright

Domino gate structure Domino OR gate Modern VLSI Design 3 e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR

Domino phases Controlled by clock . n Precharge: p-type pullup precharges the storage node;

Domino phases Controlled by clock . n Precharge: p-type pullup precharges the storage node; inverter ensures that output goes low. n Evaluate: storage node may be pulled down, so output goes up. n Modern VLSI Design 3 e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR

Domino buffer n Output inverter is needed for two reasons: – make sure that

Domino buffer n Output inverter is needed for two reasons: – make sure that outputs start low, go high so that domino output can be connected to another domino gate; – protects storage node from outside influence. Modern VLSI Design 3 e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR

Domino operation Modern VLSI Design 3 e: Chapter 3 Copyright 1998, 2002 Prentice Hall

Domino operation Modern VLSI Design 3 e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR

Domino effect Gate outputs fall in sequence: gate 1 Modern VLSI Design 3 e:

Domino effect Gate outputs fall in sequence: gate 1 Modern VLSI Design 3 e: Chapter 3 gate 2 gate 3 Copyright 1998, 2002 Prentice Hall PTR

Monotonicity n Domino gates inputs must be monotonically increasing: glitch causes storage node to

Monotonicity n Domino gates inputs must be monotonically increasing: glitch causes storage node to discharge. Modern VLSI Design 3 e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR

Output buffer n Inverting buffer isolates storage node. Storage node and inverter have correlated

Output buffer n Inverting buffer isolates storage node. Storage node and inverter have correlated values. Modern VLSI Design 3 e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR

Using domino logic n Can rewrite logic expression using De Morgan’s Laws: – (a

Using domino logic n Can rewrite logic expression using De Morgan’s Laws: – (a + b)’ = a’b’ – (ab)’ = a’ + b’ n Add inverters to network inputs/outputs as required. Modern VLSI Design 3 e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR

Domino and stored charge Charge can be stored in source/drain connections between pulldowns. n

Domino and stored charge Charge can be stored in source/drain connections between pulldowns. n Stored charge can be sufficient to affect precharge node. n Can be averted by precharging the internal pulldown network nodes along with the precharge node. n Modern VLSI Design 3 e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR

Homework Sets 3 -4 Homework Set 3: Problems 2 -13, 2 -19, 2, pp.

Homework Sets 3 -4 Homework Set 3: Problems 2 -13, 2 -19, 2, pp. 106 -108 Problems 3 -1(c), 3. 2(d), 3. 7, 3. 9, 3. 12 pp. 179 -181 Due, October 16, 2006. Homework Set 4: Problems 3 -15, 3 -16, 3. 19(b), 3. 20(b), p. 182. Due, October 23, 2006. Modern VLSI Design 3 e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR