Topics n FPGA fabric architecture concepts FPGABased System

Introduction The basic structure of FPGAs known as fabrics. n There are several different ways to build an FPGA. n Two major styles of FPGA are: (i) SRAM Based FPGAs (ii) Antifuse Programmed FPGAs n FPGA-Based System Design: Chapter 3 Copyright 2004 Prentice Hall PTR

Elements of an FPGA fabric Three major types of elements in FPGA are: n Combinational Logic. n Interconnect. n I/O pins. FPGA-Based System Design: Chapter 3 IOB LE … LE interconnect LE LE LE … LE LE LE Copyright 2004 Prentice Hall PTR

Terminology Configuration: bits that determine logic function + interconnect. n CLB: combinational logic block = logic element (LE). n LUT: Lookup table = SRAM used for truth table. n I/O block (IOB): I/O pin + associated logic and electronics. n FPGA-Based System Design: Chapter 3 Copyright 2004 Prentice Hall PTR

Logic element n Programmable: – Input connections. – Internal function. n Coarser-grained than logic gates. – Typically 4 inputs. Generally includes register. n May provide specialized logic. n – Adder carry chain. FPGA-Based System Design: Chapter 3 Copyright 2004 Prentice Hall PTR

Example logic element n a b Lookup table: a b 0 0010 memory 1001

Logic synthesis How do we break the function into logic elements? n How do

Placement n Where do we put each piece of logic in the array of

Programmable wiring n Organized into channels. – Many wires per channel. Connections between wires made at programmable interconnection points. n Must choose: n – Channels from source to destination. – Wires within the channels. FPGA-Based System Design: Chapter 3 Copyright 2004 Prentice Hall PTR

Programmable interconnection point D FPGA-Based System Design: Chapter 3 Q Copyright 2004 Prentice Hall

Programmable wiring paths FPGA-Based System Design: Chapter 3 Copyright 2004 Prentice Hall PTR

Choosing a path LE LE FPGA-Based System Design: Chapter 3 Copyright 2004 Prentice Hall

Routing problems n Global routing: – Which combination of channels? n Local routing: – Which wire in each channel? n Routing metrics: – Net length. – Delay. FPGA-Based System Design: Chapter 3 Copyright 2004 Prentice Hall PTR

Segmented wiring Length 1 Length 2 FPGA-Based System Design: Chapter 3 Copyright 2004 Prentice

Offset segments FPGA-Based System Design: Chapter 3 Copyright 2004 Prentice Hall PTR

I/O Fundamental selection: input, output, threestate? n Additional features: n – Register. – Voltage

Programming technologies n SRAM. – Can be programmed many times. – Must be programmed at power-up. n Antifuse. – Programmed once. n Flash. – Similar to SRAM but using flash memory. FPGA-Based System Design: Chapter 3 Copyright 2004 Prentice Hall PTR

Programmable switch technology SRAM Anti-fuse Switch by default is OFF; when programmed it is ON. Advantages: • negligible delay • small area overhead Disadvantages: • not really reconfigurable; one time programmable FPGA-Based System Design: Chapter 3 Flash Switch by default is ON; when programmed it is OFF. Advantages: • programming not lost when device is turned off. Disadvantages: • requires more manufacturing steps SRAM bit cell stores the programmability of the device Advantages: • can be reconfigured quickly and as repeatedly as required • no special fabrication steps Disadvantages: • takes more area • loses charge when turned off Copyright 2004 Prentice Hall PTR

Configuration n Must set control bits for: – LE. – Interconnect. – I/O blocks. n Usually configured off-line. – Separate burn-in step (antifuse). – At power-up (SRAM). FPGA-Based System Design: Chapter 3 Copyright 2004 Prentice Hall PTR

Configuration vs. programming n FPGA configuration: – Bits stay at the device they program. – A configuration bit controls a switch or a logic bit. FPGA-Based System Design: Chapter 3 n CPU programming: – Instructions are fetched from a memory. – Instructions select complex operations. add r 1, r 2 add. IR r 1, r 2 memory CPU Copyright 2004 Prentice Hall PTR

Reconfiguration n Some FPGAs are designed for fast configuration. – A few clock cycles, not thousands of clock cycles. n Allows hardware to be changed on-the-fly. FPGA-Based System Design: Chapter 3 Copyright 2004 Prentice Hall PTR

FPGA fabric architecture questions n Given limited area budget: – How many logic elements? – How much interconnect? – How many I/O blocks? FPGA-Based System Design: Chapter 3 Copyright 2004 Prentice Hall PTR

Logic element questions How many inputs? n How many functions? n – All functions of n inputs or eliminate some combinations? – What inputs go to what pieces of the function? n Any specialized logic? – Adder, etc. n What register features? FPGA-Based System Design: Chapter 3 Copyright 2004 Prentice Hall PTR

Interconnect questions How many wires in each channel? n Uniform distribution of wiring? n How should wires be segmented? n How rich is interconnect between channels? n How long is the average wire? n How much buffering do we add to wires? n FPGA-Based System Design: Chapter 3 Copyright 2004 Prentice Hall PTR

I/O block questions n How many pins? – Maximum number of pins determined by package type. Are pins programmed individually or in groups? n Can all pins perform all functions? n How many logic families do we support? n FPGA-Based System Design: Chapter 3 Copyright 2004 Prentice Hall PTR