Topics Combinational network delay n Combinational network energypower

Delay characteristics Measured from change in inputs to change in ouputs. n Data-dependent: n – Some inputs give longer delays than others. n May exercise different paths through the network. FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR

Timing diagram tc >= tx + ty A B 0 1 S C X

Sources of delay n Gate delay: – intrinsic; – drive; – load. n Wire:

Basic gate delay model Gate delay tg. n Wire delay tw. n LE FPGA-Based

Optimizing a single link n Custom design---improve gate delay: – Transistor sizing. – Gate topology. n FPGA or custom design---improve wire delay: – Shorten wire length. – Choose wire category. – Increase driver size. FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR

Fanout n Fanout adds capacitance. sink source sink FPGA-Based System Design: Chapter 4 Copyright

Driving fanout n Adding gates adds capacitance: FPGA-Based System Design: Chapter 4 Copyright 2004

Ways to drive large fanout Increase sizes of driver transistors. Must take into account rules for driving large loads. n Add intermediate buffers. This may require/allow restructuring of the logic. n FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR

Buffers FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR

Wire capacitance Use layers with lower capacitance. n Redesign layout to reduce length of

Path delay Combinational network delay is measured over paths through network. n Can trace a causality chain from inputs to worst-case output. n FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR

Path delay example network graph model FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice

Critical path = path which creates longest delay. n Can trace transistions which cause delays that are elements of the critical delay path. n FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR

Delay model Nodes represent gates. n Assign delays to edges—signal may have different delay to different sinks. n Lump gate and wire delay into a single value. n FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR

Critical path through delay graph FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall

Reducing critical path length To reduce circuit delay, must speed up the critical path—reducing delay off the path doesn’t help. n There may be more than one path of the same delay. Must speed up all equivalent paths to speed up circuit. n Must speed up cutset through critical path. n FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR

False paths Logic gates are not simple nodes—some input changes don’t cause output changes. n A false path is a path which cannot be exercised due to Boolean gate conditions. n False paths cause pessimistic delay estimates. n FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR

False path example FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR

Another false path example d = 10 d = 20 FPGA-Based System Design: Chapter

Placement and delay Placement helps determine routing. n Routing determines wire length. n Wire length determines capacitive load. n FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR

Placement and wire capacitance g 1 g 3 g 2 g 4 dvr unbalanced

Optimizing network delay Identify the longest path. n Improve delay along the longest path: n – Driver delay. – Wire delay. – Logic restructuring. FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR

Example: adder placement and delay n N-bit adder: + FPGA-Based System Design: Chapter 4

Bad placement and routing placement FPGA-Based System Design: Chapter 4 routing Copyright 2004 Prentice

Better placement and routing placement FPGA-Based System Design: Chapter 4 routing Copyright 2004 Prentice

Logic rewrites deep logic FPGA-Based System Design: Chapter 4 shallow logic Copyright 2004 Prentice

Logic transformations n Can rewrite by using subexpressions. – Simplifications affect the cost of rewrites. Flattening logic increases gate fanin. n Logic rewrites may affect gate placement. n FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR

Power optimization Transitions cause power consumption. n Logic network design helps control power consumption: n – minimizing capacitance; – eliminating unnecessary glitches. FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR

Glitching example n Gate network: FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall

Glitching example behavior n NOR gate produces 0 output at beginning and end: – beginning: bottom input is 1; – end: NAND output is 1; n Difference in delay between application of primary inputs and generation of new NAND output causes glitch. FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR

Adder chain glitching bad FPGA-Based System Design: Chapter 4 good Copyright 2004 Prentice Hall

Explanation Unbalanced chain has signals arriving at different times at each adder. n A glitch downstream propagates all the way upstream. n Balanced tree introduces multiple glitches simultaneously, reducing total glitch activity. n FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR

Power estimation tools n Power estimator approximates power consumption from: – gate network; – primary input transition probabilities; – capacitive loading. n May be switch/logic simulation based or use statistical models. FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR

Factorization for low power n Proper factorization reduces glitching. bad FPGA-Based System Design: Chapter

Factorization techniques In example, a has high transition probability, b and c low probabilities. n Reduce number of logic levels through which high-probability signals must travel in order to reduce propagation of glitches. n FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR

Layout for low power Place and route to minimize capacitance of nodes with high glitching activity. n Feed back wiring capacitance values to power analysis for better estimates. n FPGA-Based System Design: Chapter 4 Copyright 2004 Prentice Hall PTR