Topic IIa Instruction Set Architecture and MIPS Introduction

Topic IIa Instruction Set Architecture and MIPS Introduction to Computer Systems Engineering (CPEG 323) 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 1

Reading List • Slides: Topic 2 a • Henn & Patt: Chapter 2 • Other papers as assigned in class or homeworks 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 2

MIPS R 4000 Processor Internal Block Diagram System Control CP 0 Exception / Control Registers Memory Management Registers Translation Look-Aside Buffer S-Cache Controller Data Cache P-Cache Controller CPU Instruction Cache FPU CPU Registers ALU Load Aligner / Store Driver Integer Multiplier / Divider FPU Registers Pipeline Bypass FP Multiplier FP Divider FP add convert sq root Address Unit PC Incrementer Pipeline Control 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 4

Registers • 32 regs with R 0 = 0 • Reserved registers : R 1, R 26, R 27. • Special usage: R 28: R 29: R 30: R 31: 10/22/2021 pointer to global area stack pointer frame pointer return address coursecpeg 323 -08 FTopic 2 a-323. ppt 5

Standard Register Conventions • The 32 integer registers in the MIPS are “general-purpose” – any can be used as an operand or result of an arithmetic op • But making different pieces of software work together is easier if certain conventions are followed concerning which registers are to be used for what purposes. • These conventions are usually suggested by the vendor and supported by the compilers 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 6

Register Conventions in the MIPS 10/22/2021 Names Regs Purpose $zero 0 Constant 0 - 1 (Reserved for assembler) $v 0 -$v 1 2 -3 Return values/expression eval $a 0 -$a 3 4 -7 Args to functions $t 0 -$t 9 8 -15, 24 -25 $s 0 -$s 7 16 -23 Saved values - 26 -27 (Reserved for OS kernel) Temporaries (NOT SAVED) $gp 28 Global pointer $sp 29 Stack pointer $fp 30 Frame pointer $ra 31 Return address coursecpeg 323 -08 FTopic 2 a-323. ppt 7

MIPS registers and usage convention 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 8

MIPS Operations • Load/Store • ALU ops • Branches/Jumps 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 9

MIPS Instruction Formats R-Format op rs 6 bits 5 bits rt 5 bits I-Format op rs rt 6 bits 5 bits J-Format op 6 bits 10/22/2021 rd 5 bits shamt 5 bits funct 6 bits address 16 bits address 26 bits coursecpeg 323 -08 FTopic 2 a-323. ppt 10

Machine Representation of MIPS Insrtuctions MIPS fields are given names to make them easier to discuss: op rs rt rd shamt funct 6 bits 5 bits 6 bits Here is the meaning of each name of the fields in MIPS instructions: • op: operation of the instruction • rs: the first register source operand • rt: the second register source operand • rd: the register destination operand; it gets the result of the operation • shamt: shift amount • funct: function; this field selects the variant of the operation in the op field 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 12

ALU ops • R-type: ADD R 1, R 2, R 3 effect: R 1= R 2 + R 3 • Example (in MIPS assembler form): ADD $t 0, $s 1, $s 2 Decimal representation: 0 17 18 8 0 32 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 13

Machine representation (cont’d) Decimal representation 0 6 bits 17 18 8 0 32 5 bits 6 bits Binary representation: 000000 6 bits 10/22/2021 10001 10010 01000 00000 100000 5 bits 6 bits coursecpeg 323 -08 FTopic 2 a-323. ppt 14

Integer Multiply and Divide in MIPS • Multiplying two 32 -bit numbers can result in up to 64 bits • Integer division creates a quotient and remainder • MIPS has two special regs: hi and lo - Multiply results: lower bits go to lo, upper to hi - Divide results: quotient goes to lo, remainder to hi * Use extra ops (such as mflo) to move lo & hi to GPRs. 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 15

Data Transfer Instructions • I-type (base + 16 bit offsets) op rs rt 6 bits 5 bits base dest address 16 bits offset Example; lw t 0, 8 ($s 3) --- # Temporary reg t 0 gets A[8] Note: s 3 stores the start address of array A Also, rs is the base register ($S 3 in this case – also called index register), rt (in this case $t 0) stores the result (as destination register). 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 16

An Example MIPS Does A=(B+C)+(D+E) 10/22/2021 Assembly op rs rt lw $8, 48($0) 35 0 8 48 lw $9, 76($0) 35 0 9 76 add $8, $9 0 8 9 lw $9, 20($0) 35 0 9 20 lw $10, 32($0) 35 0 10 32 add $9, $10 0 9 10 9 0 32 add $8, $9 0 8 9 8 0 32 sw $8, 100($0) 43 0 8 coursecpeg 323 -08 FTopic 2 a-323. ppt rd 8 sh. 0 Ft. 32 100 17

Branches • In most processors, the “Program Counter” (PC) holds the address of the next instruction; fetch from M[(PC)] • Normally, after an instruction is finished, the CPU adds n to the PC, where n is the number of bytes in the instruction. • Branches allow a program to start fetching from a different place. • Branches are used to implement all the control-flow commands of high-level languages, such as if-then-else, for, switch, etc. 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 18

Branch Classification Two basic types of branches: Unconditional: Always jump to the specified address Conditional: Jump to the specified address if some condition is true; otherwise, continue with the next instruction Destination addresses can be specified in the same way as other operands (combination of registers, immediate constants, and memory locations), depending on what is supported in the ISA. 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 19

Branch Compilation Example Compile the following: i=j i == j? i j if ( i == j) Else: f=g+h f=g-h f = g + h; else f = g – h; Exit: 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 20

If-Then-Else in MIPS Assume f, g, h, i, j in R 8 -R 12 (respectively) bne $11, $12, Else 10/22/2021 # Branch if i<>j add $8, $9, $10 # f = g + h; j Exit # Jump to Exit Else: sub $8, $9, $10 # f = g – h; Exit: … # Code after if coursecpeg 323 -08 FTopic 2 a-323. ppt 21

Observation on Branches • Most conditional branches go a short and constant distance • Fancy addressing modes not often used • No use for auto-increment/decrement So in keeping with the RISC philosophy of simplicity, MIPS has only a few basic branch types. 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 22

MIPS Branch Types Conditional branch: beq/bne reg 1, reg 2, addr - If reg 1 =/ reg 2, jump to PC + addr (PC-relative) Register jump: jr reg - Fetch address from specified register, and jump to it Unconditional branch: j addr - Always jump to addr (use “pseudodirect” addressing) 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 23

Generating Branch Targets in MIPS 4 PC-relative addressing op rt Address rs PC Memory + 5 Pseudodirect addressing op Address PC 10/22/2021 Word Memory : coursecpeg 323 -08 FTopic 2 a-323. ppt Word 24

Branch Instructions • Conditional branches - beq R 1 , R 2 , L 1 # if R 1 = R 2 go to L 1 - bne R 1 , R 2 , L 1 # if R 1 == R 2 go to L 1 These are R-type instructions • Unconditional branches JR R 8 • Test if < 0 10/22/2021 # Jump based on register 8 slt R 1, R 16, R 17 # R 1 gets 1 if R 16 < R 17 (slt: set-less-than) bne R 1, 0, less # branch to less if R 1 == 0 coursecpeg 323 -08 FTopic 2 a-323. ppt 25

Compiling Other Control Statements Loops: • • for, while: test before loop body; jump past loop body if false Do: test condition at end of loop body; jump to beginning if true Switch: (called “case” statements in some other languages) 10/22/2021 • Build a table of addresses • Use jr (or equiv. In non-MIPS processor) • Be sure to check for default and unused cases! coursecpeg 323 -08 FTopic 2 a-323. ppt 26

Switch Compilation Example Compile the following: switch (k) { case 0: f = f + 1; break; case 1: f = f – 2; break; case 3: f = -f; break; } Note the gap (case 2); 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 27

Switch Body in MIPS L 0: L 1: L 3: addi $8, 1 j Exit subi $8, 2 j Exit sub $8, $0, $8 j Exit add immed. 1 to r 8 (f) jump to Exit (break) subtract imm. 2 from r 8 Another break f = 0 - f Another break Build the lookup table in memory: 1000 address of L 0 1004 address of L 1 1008 address of Exit 1012 address of L 3 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 28

Switch Compiled for MIPS (Assume k in r 13) slti $14, $13, 0 # set r 14 if r 13 lt 0 bne $14, $0, Exit # Go to Exit if k < 0 slti $14, $13, 4 # set r 14 if k < 4 beq $14, $0, Exit # Go to Exit if k 4 add $14, $13 # r 14 = 2*k add $14, $14 # r 14 = 4*k lw $14, 1000 ($14) # Base of table at 1000 jr $14 # Jump to the address 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 29

Instructions Supporting Procedure Calls • Jump and link jal procedure address note: return address is stored in R 31 • Return jr R 31 • Saving return address on stack R 29 is used as stack pointer • Parameter passing R 4 ~ R 7 are used for these 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 30

Other MIPS Addressing Style • Constant or immediate operands lw R 24, Addr. Constant 4(0) addi R 3, R 4, 5 (I type) constants are 16 -bit long lui R 8 255 load-upper-immediate • J-type J 10000 # goto location 10000 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 31

MIPS operands MIPS assembly language 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 32

MIPS machine language 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 33

Function Calls in the MIPS • Function calls an essential feature of programming languages - The program calls a function to perform some task - When the function is done, the CPU continues where it left off in the calling program • But how do we know where we left off? 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 34

Calling a Function in the MIPS • Use the jal (“jump and link”) instruction • jal addr just like “ j addr “ except - The “return address” (PC) + 4 placed in R 31 - This is the address of the next instruction after the jal - Use jr $31 to return 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 35

Call Example Caller Callee add $4, $0, 1000 F: lw $6, 0($4) add $5, $0, 1200 lw $7, 0($5) add $1, $0, 1 sw $6, 0($5) sw $1, 0($4) sw $7, 0($4) add $1, $1 jr $31 sw $1, 0 ($5) jal F sub $1, $2 What does F do? 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 36

Difficulties with Function Calls • This example works OK. But what if: - - The function F calls another function? The caller had something important in regs R 6 and/or R 7? The called function calls itself? • Each version of a function should have its own copies of variables • These arranged in a stack, as a pile of frames. 10/22/2021 coursecpeg 323 -08 FTopic 2 a-323. ppt 37

Stack Example Assume function A calls B, which calls C. Function C calls itself once: A’s vars start A 10/22/2021 B’s vars A calls B C’s vars B’s vars A’s vars B calls C coursecpeg 323 -08 FTopic 2 a-323. ppt D’s vars C’s vars B’s vars A’s vars C calls D 38