Topic 9 Control Flow COS 320 Compiling Techniques

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Topic 9: Control Flow COS 320 Compiling Techniques Princeton University Spring 2016 Lennart Beringer

Topic 9: Control Flow COS 320 Compiling Techniques Princeton University Spring 2016 Lennart Beringer 1

The Front End

The Front End

The Back End (Intel-HP codename for “Itanium”; uses compiler to identify parallelism)

The Back End (Intel-HP codename for “Itanium”; uses compiler to identify parallelism)

Optimization r 1 holds loop index i load address of array a load constant

Optimization r 1 holds loop index i load address of array a load constant 4 calculate offset for index i calculate address of a[i] load content of x store x in a[i] increment loop counter i repeat, unless exit condition ho can we optimize this code for code size/speed/resource usage/…?

Optimization r 1 holds loop index i load address of array a load constant

Optimization r 1 holds loop index i load address of array a load constant 4 calculate offset for index i calculate address of a[i] load content of x store x in a[i] increment loop counter i repeat, unless exit condition ho Instructions not dependent of iteration count… …can be moved outside the loop!

Register Allocation Q: can any of the registers be shared/reused? – analyze liveness/def-use

Register Allocation Q: can any of the registers be shared/reused? – analyze liveness/def-use

Register Allocation Q: can any of the registers be shared/reused? – analyze liveness/def-use A:

Register Allocation Q: can any of the registers be shared/reused? – analyze liveness/def-use A: registers r 4 and r 5 don’t overlap – can map to same register, say r 5! Then, rename r 6 to r 4.

Scheduling Q: can we exploit this?

Scheduling Q: can we exploit this?

Scheduling A: can use the “empty slot” to execute some other instruction A, as

Scheduling A: can use the “empty slot” to execute some other instruction A, as long as A is independent (does not consume the value in r 5)

Scheduling Can use the “empty slot” to execute some other instruction A, as long

Scheduling Can use the “empty slot” to execute some other instruction A, as long as A is independent (does not consume the value in r 5)

Backend analyses and tranformations e. g. loop-invariant code removal

Backend analyses and tranformations e. g. loop-invariant code removal

Control Flow Analysis

Control Flow Analysis

Control Flow Analysis Example 1 2 3 4 5 6 7 8

Control Flow Analysis Example 1 2 3 4 5 6 7 8

Control Flow Analysis Example 1 1 2 3 4 5 6 2 3 7

Control Flow Analysis Example 1 1 2 3 4 5 6 2 3 7 5 8 6 4 7 8

Basic Blocks labels and jumps mentioned in previous lecture now omitted for simp

Basic Blocks labels and jumps mentioned in previous lecture now omitted for simp

CFG of Basic Blocks CFG: Start 1 BB 1 2 1 BB 2 BB

CFG of Basic Blocks CFG: Start 1 BB 1 2 1 BB 2 BB 4 3 4 5 BB 3 2 BB 5 3 4 5 End

Domination Motivation 1. propagate r 1=4 2. exploit 4+5=9 “constant folding” assume r 1

Domination Motivation 1. propagate r 1=4 2. exploit 4+5=9 “constant folding” assume r 1 dead here

Domination Motivation 1. propagate r 1=4 2. exploit 4+5=9 “constant folding” assume r 1

Domination Motivation 1. propagate r 1=4 2. exploit 4+5=9 “constant folding” assume r 1 dead here What about this:

Domination Motivation 1. propagate r 1=4 2. exploit 4+5=9 What about this: Illegal if

Domination Motivation 1. propagate r 1=4 2. exploit 4+5=9 What about this: Illegal if r 1=4 does not hold in the other incoming arc! -Need to analyze which basic blocks are guaranteed to have

Dominator Analysis

Dominator Analysis

Dominator Analysis

Dominator Analysis

Dominator Analysis starting point: n dominated by all nodes that dominate all predecessors of

Dominator Analysis starting point: n dominated by all nodes that dominate all predecessors of n

Dominator Analysis Example s 0= Task: fill in column Dom[n]

Dominator Analysis Example s 0= Task: fill in column Dom[n]

Dominator Analysis Example s 0= More concise information: immediate dominators/dominator tr

Dominator Analysis Example s 0= More concise information: immediate dominators/dominator tr

Dominator Analysis Example Hence: last dominator of n on any path from s 0

Dominator Analysis Example Hence: last dominator of n on any path from s 0 to n is IDom[n] Task: fill in column IDom[n]

Dominator Analysis Example Hence: last dominator of n on any path from s 0

Dominator Analysis Example Hence: last dominator of n on any path from s 0 to n is IDom[n] 1 2 2 2 4 2 5 8 9 7 2

Use of Immediate Dominators: Dominator Tree Immediate dominators can be arranged in tree n:

Use of Immediate Dominators: Dominator Tree Immediate dominators can be arranged in tree n: the nodes m such that n=IDom[m • children of node • root: s 0 • hence: each node dominates only its tree descendants s 0=1 2 3 4 5 7 6 8 11 12 9 10 (note: some tree arcs are CFG edges, some

Post Dominator

Post Dominator

Loop Optimization

Loop Optimization

Examples of Loops 1 1 2 2 1 2 3 4 5 6

Examples of Loops 1 1 2 2 1 2 3 4 5 6

Examples of Loops 1 1 2 2 1 2 3 4 Header node: 1

Examples of Loops 1 1 2 2 1 2 3 4 Header node: 1 3 4 5 6 Two loops, with identical header node: 1 Header node: 2

Back Edges Back-edges: 3 2, 4 2, 9 8, 10 5

Back Edges Back-edges: 3 2, 4 2, 9 8, 10 5

Natural Loops Back-edge 3 2 4 2 9 8 10 5 Header of nat.

Natural Loops Back-edge 3 2 4 2 9 8 10 5 Header of nat. loop Nodes

Natural Loops Back-edge Header of nat. loop Nodes 3 2 2 2, 3 4

Natural Loops Back-edge Header of nat. loop Nodes 3 2 2 2, 3 4 2 2 2, 4 9 8 8 8, 9 10 5 5 5, 8, 9, 10 Q: Suppose we had an additional edge 5 3 – is this a backedge?

Natural Loops Back-edge Header of nat. loop Nodes 3 2 2 2, 3 4

Natural Loops Back-edge Header of nat. loop Nodes 3 2 2 2, 3 4 2 2 2, 4 9 8 8 8, 9 10 5 5 5, 8, 9, 10 Q: Suppose we had an additional edge 5 3 – is this a backedge? A: No! 3 does not dominate 5!

Loop Optimization

Loop Optimization

Loop Optimization This CFG does not contain a loop! 2 1 3 {1, 2,

Loop Optimization This CFG does not contain a loop! 2 1 3 {1, 2, 3} is not a loop: • 1 is not a header: there are no paths/arcs back to 1 • 2 is not a header: it does not dominate 1 or 3 • similarly for 3 {2, 3} is not a loop: • 2 is not a header: it does not dominate 3

Loop Optimization “into the edge” leading to the header.

Loop Optimization “into the edge” leading to the header.

Loop Optimization the loop increment/decrement i, and by a loop-independent valu Q: is there

Loop Optimization the loop increment/decrement i, and by a loop-independent valu Q: is there an induction variable here?

Loop Optimization the loop increment/decrement i, and by a loop-independent valu ex plo it

Loop Optimization the loop increment/decrement i, and by a loop-independent valu ex plo it h ere ? ! holds here r 1 1 2 3 4 r 4 0 4 8 12 r 1 is induction variable!

Loop Optimization the loop increment/decrement I, by a loop-independent value. r 4 = -4

Loop Optimization the loop increment/decrement I, by a loop-independent value. r 4 = -4 r 4 = r 4 + 4 // replace * by + r 4 <= 40 r 1 1 2 3 4 r 4 0 4 8 12 minated r 1 and r 3, cut 2 instructions; made 1 instruction 1 cycle faste

Non-Loop Cycles Remember: this CFG does not contain a loop! 1 eduction: collapse nodes,

Non-Loop Cycles Remember: this CFG does not contain a loop! 1 eduction: collapse nodes, eliminate edges 2 3

Node Splitting 1 2 1. duplicate a node of the cycle, say 2 3

Node Splitting 1 2 1. duplicate a node of the cycle, say 2 3 1 2’ 2 3

Node Splitting 1 2 1. duplicate a node of the cycle, say 2 3

Node Splitting 1 2 1. duplicate a node of the cycle, say 2 3 2. connect the copy to its successor and predecessor 1 2’ 2 3

Node Splitting 1 2 1. duplicate a node of the cycle, say 2 3

Node Splitting 1 2 1. duplicate a node of the cycle, say 2 3 1 2’ 2. connect the 2 copy to its successor and predecessor 3. the successor of the copy is the loop header! 3

Reduction Collapse nodes, eliminate edges 1 A 4 2 B 5 6 7 3

Reduction Collapse nodes, eliminate edges 1 A 4 2 B 5 6 7 3 8 A 9 C B C