Topic 6 Bitwise Instructions CSE 30 Computer Organization

Topic 6: Bitwise Instructions CSE 30: Computer Organization and Systems Programming Winter 2010 Prof. Ryan Kastner Dept. of Computer Science and Engineering University of California, San Diego

Overview v. Logic Instructions v. Shifts and Rotates v. ARM Arithmetic Datapath

Logical Operators v. Basic logical operators: v. AND: outputs 1 only if both inputs are 1 v. OR: outputs 1 if at least one input is 1 v. XOR: outputs 1 if exactly one input is 1 v. In general, can define them to accept >2 inputs, but in the case of ARM assembly, both of these accept exactly 2 inputs and produce 1 output v. Again, rigid syntax, simpler hardware

Logical Operators v. Truth Table: standard table listing all possible combinations of inputs and resultant output for each v. Truth Table for AND, OR and XOR A 0 0 1 1 B 0 1 A AND B 0 0 0 1 A OR B A XOR B A BIC B 0 0 1 1 1 0

Uses for Logical Operators that ANDing a bit with 0 produces a 0 at the output while ANDing a bit with 1 produces the original bit. v. This can be used to create a mask. v. Note v. Example: mask: v. The 1011 0110 1010 0100 0011 1101 1010 0000 0000 1111 result of ANDing these: 0000 0000 1101 1010 mask last 12 bits

Uses for Logical Operators note that ORing a bit with 1 produces a 1 at the output while ORing a bit with 0 produces the original bit. v. This can be used to force certain bits of a string to 1 s. v. Similarly, v. For example, 0 x 12345678 OR 0 x 0000 FFF results in 0 x 1234 FFFF (e. g. the high-order 16 bits are untouched, while the low-order 16 bits are forced to 1 s).

Uses for Logical Operators note that XORing a bit with 1 produces flips the bit (0 -> 1, 1 -> 0) at the output while XORing a bit with 0 produces the original bit. v. This can be used to force certain bits of a string to 1 s. v. Additionally, v. For example, 0 x 12345678 OR 0 x 0000 FFF results in 0 x 1234 FFFF (e. g. the high-order 16 bits are untouched, while the low-order 16 bits are forced to 1 s).

Uses for Logical Operators note that BICing a bit with 1 resets the bit (sets to 0) at the output while BICing a bit with 0 produces the original bit. v. This can be used to force certain bits of a string to 0 s. v. Finally, v. For example, 0 x 12345678 OR 0 x 0000 FFFF results in 0 x 12340000 (e. g. the high-order 16 bits are untouched, while the low-order 16 bits are forced to 0 s).

Bitwise Logic Instruction Syntax v. Syntax of Instructions: 1 2, 3, 4 where: 1) instruction by name 2) operand getting result (“destination”) 3) 1 st operand for operation (“source 1”) 4) 2 nd operand for operation (“source 2”) v. Syntax v 1 is rigid (for the most part): operator, 3 operands v. Why? Keep Hardware simple via regularity

Bitwise Logic Operations v. Bitwise AND in Assembly v. Example: AND r 0, r 1, r 2 (in ARM) Equivalent to: a = b & c (in C) where ARM registers r 0, r 1, r 2 are associated with C variables a, b, c v. Bitwise OR in Assembly v. Example: ORR r 3, r 4, r 5 (in ARM) Equivalent to: d = e | f (in C) where ARM registers r 3, r 4, r 5 are associated with C variables d, e, f

Bitwise Logic Operations v. Bitwise XOR in Assembly v. Example: EOR r 0, r 1, r 2 (in ARM) Equivalent to: a = b ^ c (in C) where ARM registers r 0, r 1, r 2 are associated with C variables a, b, c v. Bitwise Clear in Assembly v. Example: BIC r 3, r 4, r 5 (in ARM) Equivalent to: d = e & (!f) (in C) where ARM registers r 3, r 4, r 5 are associated with C variables d, e, f

Assignment Instructions v Assignment in Assembly v. Example: MOV r 0, r 1 (in ARM) Equivalent to: a = b (in C) where ARM registers r 0 are associated with C variables a v. Example: MOV r 0, #10 Equivalent to: a = 10 (in ARM) (in C)

Assignment Instructions v MVN – Move Negative – moves one complement of the operand into the register. v Assignment in Assembly v. Example: MVN r 0, #0 (in ARM) Equivalent to: a = -1 (in C) where ARM registers r 0 are associated with C variables a Since ~0 x 0000 == 0 x. FFFF

Shifts and Rotates v LSL – logical shift by n bits – multiplication by 2 n C v … C ASR – logical shift by n bits – signed division by 2 n … v 0 LSR – logical shift by n bits – unsigned division by 2 n 0 v … C ROR – logical shift by n bits – 32 bit rotate … C

Shifts and Rotates v Shifting in Assembly Examples: MOV v Rotating r 4, r 6, LSL #4 ; r 4 = r 6 << 4 r 4, r 6, LSR #8 ; r 4 = r 6 >> 8 in Assembly Examples: MOV r 4, r 6, ROR #12 ; r 4 = r 6 rotated right 12 bits ; r 4 = r 6 rotated left by 20 bits (32 -12) Therefore no need for rotate left.

Variable Shifts and Rotates v Also possible to shift by the value of a register v Examples: MOV r 4, r 6, LSL r 3 ; r 4 = r 6 << value specified in r 3 MOV r 4, r 6, LSR #8 ; r 4 = r 6 >> 8 v Rotating in Assembly v. Examples: MOV r 4, r 6, ROR #12 ; r 4 = r 6 rotated right 12 bits ; r 4 = r 6 rotated left by 20 bits (32 -12) Therefore no need for rotate left.

Constant Multiplication v Constant multiplication is often faster using shifts and additions MUL r 0, r 2, #8 ; r 0 = r 2 * 8 Is the same as: MOV r 0, r 2, LSL #3 ; r 0 = r 2 * 8 v Constant division MOV r 1, r 3, ASR #7 ; r 1 = r 3/128 Vs. MOV r 1, r 3, LSR #7 ; r 1 = r 3/128 The first treats the registers like signed values (shifts in MSB). Thelatter treats data like unsigned values (shifts in 0). int vs unsigned int >>

Constant Multiplication v Constant multiplication with subtractions MUL r 0, r 2, #7 ; r 0 = r 2 * 7 Is the same as: RSB r 0, r 2, LSL #3 ; r 0 = r 2 * 7 ; r 0 = -r 2 + 8*r 2 = 7*r 2 RSB r 0, r 1, r 2 is the same as SUB r 0, r 2, r 1 ; r 0 = r 1 – r 2 Multiply by 35: ADD r 9, r 8, LSL #2 RSB r 10, r 9, LSL #3 ; r 9=r 8*5 ; r 10=r 9*7 Why have RSB? B/C only the second source operand can be shifted.

Using a Barrel Shifter Register, optionally with shift operation Operand 1 2 Barrel Shifter v Shift value can be either be: 5 bit unsigned integer v Specified in bottom byte of another register. v v Used for multiplication by constant Immediate value v ALU Result 8 bit number, with a range of 0 -255. v Rotated right through even number of positions v Allows increased range of 32 bit constants to be loaded directly into registers

Loading Constants v Constants can only be 8 bit numbers v Allows assignment of numbers between 0 -255 or [0 x 00 – 0 x. FF] v Why? Constants stored in code and there is limited space (only 32 bits). v Assignment v. Example: in Assembly MOV r 0, #0 x. FF (in ARM) Equivalent to: a = 255 (in C) where ARM registers r 0 C variable a

Immediate Constants v The data processing instruction format has 12 bits available for operand 2 11 8 7 rot x 2 0 immed_8 Shifter ROR 0 x. FF 000000 MOV r 0, #0 x. FF, 8 v 4 bit rotate value (0 -15) is multiplied by two to give range 0 -30 in steps of 2 v Rule to remember is “ 8 -bits rotated right by an even number of bit positions”

Loading Constants Rotate Value Binary Decimal Hexadecimal 0 000000000000 xxxx 0 -255 0 -0 x. FF Right, 30 bits 00000000000 xxxx 00 4 -1020 0 x 4 -0 x 3 FC Right, 28 bits 0000000000 xxxx 0000 16 -4080 0 x 10 -0 x. FF 0 Right, 26 bits 000000000 xxxx 000000 128 -16320 0 x 40 -0 x 3 FC 0 … … Right, 8 bits xxxx 000000000000 16777216255 x 224 0 x 10000000 x. FF 000000 Right, 6 bits xxxxxx 00000000000 xx - - Right, 4 bits xxxx 00000000000 xxxx - - Right, 2 bits xx 00000000000 xxxxxx - - v This scheme can generate a lot, but not all, constants. v v v ~50% of constants between [-15, 15]; ~90% between [-512, 512] Others must be done using literal pools (more on that later)

Conclusion v. Instructions so far: v. Previously: ADD, SUB, MULA, [U|S]MULL, [U|S]MLAL v. New instructions: RSB AND, ORR, EOR, BIC MOV, MVN LSL, LSR, ASR, ROR v. Shifting can only be done on the second source operand v. Constant multiplications possible using shifts and addition/subtractions