TopDown and BottomUp Approaches to Stable Clock Synthesis
Top-Down and Bottom-Up Approaches to Stable Clock Synthesis Lecturer Michael S. Mc. Corquodale Authors Michael S. Mc. Corquodale, Mei Kim Ding, and Richard B. Brown Solid State Electronics Laboratory Center for Wireless Integrated Microsystems (WIMS) Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor, MI USA 48109 -2122 International Conference on Electronic Circuits and Systems, Sharjah, U. A. E. , 2003
Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Lecture Overview • Overview of Clock Synthesis • Effects of Frequency Translation on Frequency Stability • Top-Down and Bottom-Up Synthesis • Application • Design and Simulation • Results • Conclusions and Future Work NSF ERC for Wireless Integrated Micro. Systems (WIMS) 2
Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Clock Synthesis • • The clock is arguably the most significant signal in any synchronous system Harmonic quartz XTAL reference + PLL is the ubiquitous approach – High accuracy and stability – Broad range of output frequencies • Drawbacks – Discrete components required (not monolithic) – PLL power and area – Systemic short-term stability degradation (to be presented) • Challenges in developing an alternative (possibly monolithic) approach – Accuracy and stability – Monolithic reference (typically low-Q) NSF ERC for Wireless Integrated Micro. Systems (WIMS) 3
Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Short-Term Frequency Stability Metrics Period Jitter: s of the position of the next edge relative to the ideal Ideal tk Period Jitter tk+1 Phase Noise: Power relative to fundamental at some offset fm P fm fo f NSF ERC for Wireless Integrated Micro. Systems (WIMS) 4
Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Frequency Multiplication and Division Phase and frequency are related by a linear operator: Frequency mult. /div. results in phase noise mult. /div. : Using narrowband FM approximation: Linear freq. translation results in quadratic change in noise power NSF ERC for Wireless Integrated Micro. Systems (WIMS) 5
Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Converting Phase Noise to Period Jitter The SSB phase noise PSD can be represented by a Lorentzian function: 20 d. B/dec Which can be approximated for: fm Using the above: • Typically p fo 2 c called corner or line width: select fm above the corner and below fo • Lorentzian implies absence of flicker noise (slope must be 20 d. B/dec) NSF ERC for Wireless Integrated Micro. Systems (WIMS) 6
Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Frequency Translation and Jitter Using phase noise conversion expression, determine jitter: Considering fractional, or ppm, jitter: Frequency translation also enhances and degrades jitter NSF ERC for Wireless Integrated Micro. Systems (WIMS) 7
Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Relationship with Quality-Factor Leeson Phase Noise Model • Leeson model: Q-factor quadratically related to phase noise • Q-factor is one of the most significant metrics indicating stability • Typical quartz XTAL Q on the order of 10, 000 • Frequency translation also quadratically related to phase noise • Consider effective Q-factor modification due to freq. translation • If Ndiv. Nmult > Qmult/Qdiv then divided signal more stable • Assumption: oscillator power and noise factor are the same • Nmult for XTAL+ PLL up to 4096: high-Q, but large degradation NSF ERC for Wireless Integrated Micro. Systems (WIMS) 8
Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Frequency Translation Summary Variable/Metric Reference Oscillator Frequency Multiplication Frequency Division Output Frequency (Hz) fref Nfref /N SSB Phase Noise PSD (d. Bc/Hz) Period Jitter (s) J Relative Period Jitter (ppm) Jppm NSF ERC for Wireless Integrated Micro. Systems (WIMS) 9
Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions A Bottom-Up Approach Quartz XTAL reference oscillator + PLL fref PFD CP LPF vctrl Nfref ÷N The signal that actually drives the processor is a frequency multiplied (and degraded) image of the reference NSF ERC for Wireless Integrated Micro. Systems (WIMS) 10
Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions A Top-Down Approach A harmonic LC (and monolithic) RF reference fref ÷N fref N The signal that actually drives the processor is a frequency divided (and enhanced) image of the reference LC reference also provides good accuracy as compared to ring or relaxation approach NSF ERC for Wireless Integrated Micro. Systems (WIMS) 11
Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Application Test Bench • Intel SA-1110 – 3. 6864 MHz XTAL reference + PLL – ~200 MHz max output frequency • Bottom-up Approach – 3. 125 MHz XTAL, Q = 10, 000 – Output = 200 MHz, N = 64 All transistor design with TSMC 0. 18 MM/RF • Top-down Approach – 3. 2 GHz reference, Q = 10 – Output = 200 MHz, N = 16 NSF ERC for Wireless Integrated Micro. Systems (WIMS) 12
Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Pierce Bottom-Up XTAL Reference OSC 3. 125 MHz XTAL reference 50 1 500 k XTAL lumped parameter model 30 1 7 p 389 m 4. 79 f 30 p 900 30 p Requires off-chip XTAL + 2 capacitors + 1 resistor NSF ERC for Wireless Integrated Micro. Systems (WIMS) 13
Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Ring Bottom-Up VCO 20 -stage 200 MHz current-starved ring VCO bias from last stage 4 0. 18 2 0. 18 from last stage NSF ERC for Wireless Integrated Micro. Systems (WIMS) 14
Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions A Bottom-Up System Remainder of PLL modeled with Verilog-A fref PFD CP LPF vctrl Nfref ÷N NSF ERC for Wireless Integrated Micro. Systems (WIMS) 15
Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions LC Top-Down Reference OSC 3. 2 GHz monolithic RF LC reference oscillator bias 36 0. 18 100 0. 18 2 n. H 950 f. F 40 0. 18 NSF ERC for Wireless Integrated Micro. Systems (WIMS) 40 0. 18 16
Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Top-Down System Implementation Entire system designed at the device level 3. 2 GHz D + - AMP Q DFF D Q DFF Q Q 200 MHz Each feedback flip-flop divides frequency by two NSF ERC for Wireless Integrated Micro. Systems (WIMS) 17
Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Design and Simulation • Bottom-up Approach – Phase noise for reference OSC and VCO simulated at device level – Device-level results modeled with Verilog-A – Entire PLL modeled with phase domain approach using Verilog-A • Top-down Approach – Entire system simulated at the device level NSF ERC for Wireless Integrated Micro. Systems (WIMS) 18
Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Bottom-Up Phase Noise Performance NSF ERC for Wireless Integrated Micro. Systems (WIMS) 19
Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Bounding PLL Phase Noise NSF ERC for Wireless Integrated Micro. Systems (WIMS) 20
Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Top-Down Phase Noise Performance NSF ERC for Wireless Integrated Micro. Systems (WIMS) 21
Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions Performance Comparison Performance Metric Bottom-Up Synthesis Top-Down Synthesis Application Frequency, fo (MHz) 200 Reference Oscillator Frequency, fref (MHz) 3. 125 3, 200 Multiplication/Division Factor, N 64 16 Reference Oscillator Quality Factor, Q 10, 000 10 Reference Oscillator Phase Noise Density, (No/Po)fm (d. Bc/Hz) -140. 8 d. Bc/Hz @ 10 k. Hz -83 d. Bc/Hz @ 10 k. Hz Calculated Period Jitter at Reference from (No/Po)fm @ 10 k. Hz offset, J (fs) 233 5. 5 Calculated Relative Period Jitter at Reference, J ppm (ppm) 0. 73 18 Synthesizer Output Phase Noise Density, (No/Po)fm (d. Bc/Hz) -104. 6 d. Bc/Hz @ 10 k. Hz -106. 8 @ 10 k. Hz Calculated Period Jitter at Output from (No/Po)fm @ 10 k. Hz offset, J (fs) 29 23 Calculated Relative Period Jitter at Output J ppm (ppm) 5. 9 4. 6 Phase Noise Density Accumulation/Reduction Factor, (d. B) 36. 2 -23. 8 Period Jitter Accumulation/Reduction Factor 0. 12 4. 2 Relative Period Jitter Accumulation/Reduction Factor 8. 0 0. 23 NSF ERC for Wireless Integrated Micro. Systems (WIMS) 22
Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions and Future Work • Frequency multiplication degrades short term stability and effectively reduces reference oscillator Q • Frequency division enhances short-term stability and effectively increases reference oscillator Q • Bottom-up approach requires reference XTAL OSC + PLL while topdown approach requires only reference OSC + divider • For a common application, top-down approach provides comparable frequency stability to bottom-up approach, while being substantially simpler to implement • Top-down approach facilitates monolithic integration • Such a clock synthesis system has been developed and will be reported in the near future • More sophisticated top-down architectures will be explored NSF ERC for Wireless Integrated Micro. Systems (WIMS) 23
Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions and Future Work Questions? NSF ERC for Wireless Integrated Micro. Systems (WIMS) 24
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