TOF Electronics Qi An Fast Electronics Lab USTC

TOF Electronics Qi An Fast Electronics Lab, USTC Sept. 16~17, 2002

Two Functions • To provide a precision time measurement for Particles Identification • To provide an event timing signal used by trigger system • Time Resolution Total of TOF system: 80 ps (RMS) Uncertainty from Electronics: 25 ps (RMS)

TOF Readout Electronics • Time Measurement • Charge Measurement • Mean Timer

TOF Signal Processing. For simplicity, only a signal sector is shown

Time Measurement • • • Multi-Hit Capability Time Resolution: 25 ps (RMS) Dynamic Range: 60 ns Discriminate with Double Threshold (Low & High) HPTDC

HPTDC – High Precision General Purpose TDC (HPTDC) (J. Christiansen et al. ) – 32 -channel TDC • Bin 100, 200, 400 or 800 ps • Dynamic range about 100 ms – 8 -channel TDC (Very High Resolution Mode) • Bin 25 ps • Same dynamic range

Architecture • The Timing Unit Based On A 40 MHz Clock PLL DLL Coarse Counter RC-Delay Line • Data Processing Unit Trigger Match L 1 Buffer Read FIFO

Performance Of HPTDC

Two Options for Time Measurement • HPTDC Without Time Stretcher (TS) - It will be our first choice • HPTDC With Time Stretcher (TS) - KEK’s TS Daughter - Monolithic Integrated Time Stretcher (MTS 1)

KEK’s Clocked Time Stretcher

HPTDC With Time Stretcher • Principle of KEK’s Time Stretcher • Feasibility of HPTDC with TS Scheme ▪ HPTDC Time resolution: 100 ps ▪ Time Stretch: f = 4 ▪ 4 Time Tags (T 1, T 2, T 3 & T 4) for One TOF Hit ▪ Simultaneous Measure Leading and Trailing Edge of Signal with one channel of HPTDC ▪ Dead Time - TS Daughter board: 400 ns (included a recovery time) - MTS 1: No Dead Time with Ping Pang Mode

The Input & Output Signal of TS • Input: TOF Hit Signal and Reformance Clock • Output: Time Tag: T 1, T 2, T 3 and T 4 Δt = T 2 -T 1; fΔt = T 3 -T 2

Monolithic Time Stretcher (MTS 1)

Technical Parameters of MTS 1 • Process: Agilent 0. 5 mm CMOS, 3 metal, single poly, linear Capacitor • 8 Channels: 8 LVDS inputs & 16 LVDS outputs (2 x 8 channels) • Programmable Stretch factor: 1: 1 to 1: 20 (1: 4 will be used in BESIII) • Ping-Pong Mode • RF clock: LVDS pair (up to 100 MHz) • Package: 84 -pin TQFP Functions

Evaluation of HPTDC • Three ways of testing - HPTDC channel with KEK’s TS Daughter board - HPTDC channel with Monolithic TS chip - HPTDC channel without TS • Test Board - VME 6 U - A 32, D 32 Mode - LVDS Inputs

Charge Measurement • Functions - To correct the Effect of Time Walk • Two Options: - Amplitude Measurement - Waveform Digitization

Amplitude Measurement PMT Signal FIFO ~3. 2µs pipeline Peak Detect Events Buffers VMEBus 12 Bits FADC

Option 2: Waveform Digitizer • Analog Transient Waveform Digitizer (ATWD) (Designed by LBNL) - Four Independent Channels - Sample Rate : 0. 3~2 GSPS - Resolution: 10 Bit - 128 Analog Memories - 128 Wilkinson Type ADC with 40 MHz counter clock • Ping Pang Mode to Reduce the Dead Time

Ping Pang Mode AWTD A 4 PMT signals Output 4 2: 1 MUX Buffer ADC Output Data AWTD B 4 Disc. Outputs L 1 Trigger Trig. Logic Control Logic

40 MHz Reference Clock • Using RF Clock as t 0 instead of “Pick Up” signal for the beam collision time • Getting a 40 MHz clock from RF signal as a reference clock for HPTDC & others • The Jitters should be less than 20 ps RMS

Design Strategies for 40 MHz Clock • Using PLL technique to generate 40 MHz clock and clean up the input clock. • Using an optical transfer system with 80 m Phase Stabilized Optical Fiber (PSOF). • Using low skew & low jitter clock driver for clock distribution.

Block diagram of reference clock system

PLL: SY 89421 V Precision PLL (Micrel Semiconductor) – Input Range: • 12 MHz-560 MHz with internal VCO operation • 2 GHz with HF Inputs and External VCO – Output Range: • >1 GHz with Internal VCO • 2. 0 GHz with External VCO – Two Output Pairs: • HF Outputs (VCO Output) • F Outputs (post dividers) – External Loop Filter – Jitter: 10 ps RMS (Typ), 15 ps RMS (Max) – Internal programmable dividers offer 1 -40 range.

40 MHz clock Circuit SY 89421 V RF Signal Input Phase 500 MHz Detector VCO P-Div N-Divider 1, 2, 4, 8, 10, 12, 16, 20 N Divider = 12 P-Divider = 1 Fout = Fin /12 =40 MHz HFout 40 MHz Clock Out

NB 100 LVEP 221 Clock Fanout: 1: 20 • • • 85 ps Typical Device–to–Device Skew 20 ps Typical Output–to–Output Skew Jitter Less than 1 ps RMS Maximum Frequency > 1. 0 GHz Typical Thermally Enhanced 52–Lead LQFP VBB Output 540 ps Typical Propagation Delay LVPECL & HSTL Mode LVECL Mode

Test Board for PLL & Fannout

Total Electronics Requirements • • • FEE Boards (16 ch/board): Leading Edge Discriminators : Trigger Outputs : TDC Channels : ADC Channels : Pre_Amplifiers: 28 896 (HL & LL) 272 448 176 ( If CTTs are used )

Thanks