TK 2123 Lecture 14 Instruction Set Architecture Level

TK 2123 Lecture 14: Instruction Set Architecture Level (Level 2) Ass. Prof. Dr Masri Ayob

ISA Level n n n 3/12/2021 OS level – ISA level - Microarchitecture level. Historically, ISA level was developed before any of the other levels (originally the only level). Sometimes referred as “the architecture” of a machine or “assembly language” (incorrect). Interface between software and hardware. The ISA level defines the interface between the compilers and hardware. Prepared by: Dr Masri Ayob 2

ISA Level The ISA level is the interface between the compilers and the hardware. 3/12/2021 Prepared by: Dr Masri Ayob 3

ISA Level n Is defined by how the machine appears to a machine language programmer. n No person does machine language programming. n Redefined : n n The compiler writer has to know: n n n 3/12/2021 ISA-level code is what a compiler outputs. Memory model Registers Data type Addressing mode Instruction set. Prepared by: Dr Masri Ayob 4

Memory Models n n n 3/12/2021 What order do we read numbers that occupy more than one byte e. g. (numbers in hex to make it easy to read) 12345678 can be stored in 4 x 8 bit locations as follows Prepared by: Dr Masri Ayob 5

Memory Models (example) n Address 184 185 186 n i. e. read top down or bottom up? n n 3/12/2021 Value (1) 12 34 56 78 Prepared by: Dr Masri Ayob Value(2) 78 56 34 12 6

Memory Models n n The problem is called Endian The system on the left has the most significant byte in the smallest address: n n The system on the right has the least significant byte in the smallest address: n 3/12/2021 Big-endian Little-endian Prepared by: Dr Masri Ayob 7

Example of C Data Structure 3/12/2021 Prepared by: Dr Masri Ayob 8

Standard…What Standard? n n n 3/12/2021 Pentium (80 x 86), VAX are little-endian IBM 370, Motorola 680 x 0 (Mac), and most RISC are big-endian Internet is big-endian. Prepared by: Dr Masri Ayob 9

What is an Instruction Set? n The complete collection of instructions that are understood by a CPU n n n 3/12/2021 Machine Code Binary Usually represented by assembly codes Prepared by: Dr Masri Ayob 10

Elements of an Instruction n Operation code (Opcode) n n Source Operand reference n n Put the answer here…. . Next Instruction Reference n 3/12/2021 To this. . i. e. the data to be operated on Result Operand reference n n Do this…i. e. the task to be performed When you have done that, do this. . . Prepared by: Dr Masri Ayob 11

Where have all the Operands Gone? n n n 3/12/2021 Main memory (or virtual memory or cache) CPU register I/O device Prepared by: Dr Masri Ayob 12

Instruction Cycle State Diagram 3/12/2021 Prepared by: Dr Masri Ayob 13

Instruction Representation n n In machine code each instruction has a unique bit pattern For human consumption (well, programmers anyway) a symbolic representation is used n n Operands can also be represented in this way n n ADD A, B Usually there are not enough bits in one byte to store enough instructions and addresses: n 3/12/2021 e. g. ADD, SUB, LOAD Instructions stored in more than one byte. Prepared by: Dr Masri Ayob 14

Simple Instruction Format 3/12/2021 Prepared by: Dr Masri Ayob 15

Number of Addresses (a) n 3 addresses n n n 3/12/2021 Operand 1, Operand 2, Result a = b + c; May be a forth - next instruction (usually implicit) Not common Needs very long words to hold everything Prepared by: Dr Masri Ayob 16

Number of Addresses (b) n 2 addresses n n 3/12/2021 One address doubles as operand result a=a+b Reduces length of instruction Requires some extra work n Temporary storage to hold some results Prepared by: Dr Masri Ayob 17

Number of Addresses (c) n 1 address n n n 3/12/2021 Implicit second address Usually a register (accumulator) Common on early machines Prepared by: Dr Masri Ayob 18

Number of Addresses (d) n 0 (zero) addresses n n n 3/12/2021 All addresses implicit Uses a stack e. g. push a push b add pop c Prepared by: Dr Masri Ayob 19

How Many Addresses n More addresses n n Fewer addresses n n n 3/12/2021 More complex (powerful? ) instructions More registers n Inter-register operations are quicker Fewer instructions per program Less complex (powerful? ) instructions More instructions per program Faster fetch/execution of instructions Prepared by: Dr Masri Ayob 20

Design Decisions (1) n Operation issues: n n n Data types Instruction formats n n 3/12/2021 How many ops? What can they do? How complex are they? Length of op code field Number of addresses Prepared by: Dr Masri Ayob 21

Design Decisions (2) n Registers n n Number of CPU registers available Which operations can be performed on which registers? n Addressing modes (later…) n RISC v CISC 3/12/2021 Prepared by: Dr Masri Ayob 22

Addressing Modes n Instructions can be categorized according to their method of addressing the hardware registers and/or memory. n n n Implied Addressing Register Addressing Immediate Addressing Direct Addressing Register Indirect Addressing Combined Addressing Modes. The various ways of addressing data in an instruction are known as addressing mode. 3/12/2021 Prepared by: Dr Masri Ayob 23

Implied Addressing n The addressing mode of certain instructions is implied by the instruction’s function. n 3/12/2021 For example: n the STC (set carry flag) instruction deals only wit the carry flag n the DAA (decimal adjust accumulator) instruction deals with the accumulator. Prepared by: Dr Masri Ayob 24

Register Addressing n The accumulator is implied as a second operand. n 3/12/2021 For example, n the instruction CMP E may be interpreted as 'compare the contents of the E register with the contents of the accumulator. Prepared by: Dr Masri Ayob 25

Immediate Addressing n These instructions have data assembled as a part of the instruction itself. n 3/12/2021 For example, the instruction CPI 'C' may be interpreted as ‘compare the contents of the accumulator with the letter C. Prepared by: Dr Masri Ayob 26

Direct Addressing n n These instructions directly specify the memory address of the operand. Example: n n 3/12/2021 JMP 1000 H causes a jump to the address 1000 H by replacing the current contents of the PC with the ne value 1000 H. LDA 2000 H will load the contents of memory location 2000 H into the accumulator. Prepared by: Dr Masri Ayob 27

Register Indirect Addressing n n These instructions reference memory via a register pair. For example: MOV M, C n n 3/12/2021 moves the contents of the C register into the memor location pointed by the H and L register pair. The instruction LDAX B loads the accumulator with the byte of data specified by the address in the B and C register pair. Prepared by: Dr Masri Ayob 28

Combined Addressing Modes n Some instructions use a combination of addressing modes. n n n 3/12/2021 A CALL instruction, for example, combines direct addressing and register indirect addressing. The direct address in a CALL instruction specifies the address of the desired subroutine; the register indirect address is the stack pointer. The CALL instruction pushes the current contents of the program counter into the memory location specified by the stack pointer. . Prepared by: Dr Masri Ayob 29

Discussion of Addressing Modes A comparison of addressing modes. 3/12/2021 Prepared by: Dr Masri Ayob 30

Timing Effects of Addressing Modes n Addressing modes affect both: n n n the amount of time required for executing an instruction. the amount of memory required for its storage. For example, instructions that use implied or register addressing, execute very quickly since they deal directly with the processor’s hardware or with data already present in hardware registers. n the entire instruction can be fetched with a single memory access. The number of memory accesses required is the greatest factor i determining execution timing. 3/12/2021 Prepared by: Dr Masri Ayob 31

Timing Effects of Addressing Modes n More memory accesses require more execution time. n 3/12/2021 A CALL instruction, for example, requires five memo accesses: three to access the entire instruction and two more to push the contents of the program counter onto the stack. Prepared by: Dr Masri Ayob 32

Types of Operand n n Addresses Numbers n n Characters n n ASCII etc. Logical Data n 3/12/2021 Integer/floating point Bits or flags Prepared by: Dr Masri Ayob 33

Pentium Data Types n n n 3/12/2021 8 bit Byte 16 bit word 32 bit double word 64 bit quad word Addressing is by 8 bit unit A 32 bit double word is read at addresses divisible by 4 Prepared by: Dr Masri Ayob 34

Types of Instruction Operation n n n 3/12/2021 Data Transfer (data movement) Arithmetic Logical Conversion I/O System Control Program Control Prepared by: Dr Masri Ayob 35

Data Transfer (Data Movement) n Specify n n May be different instructions for different movements n n e. g. IBM 370 Or one instruction and different addresses n n Source Destination Amount of data e. g. VAX E. g. MOV A, B Move 8 -bit data from register B to accumulator A. 3/12/2021 Prepared by: Dr Masri Ayob 36

Data Transfer (Data Movement) n Data Movement Instructions are the most frequently used and computer designers provide a lot of flexibility to these instructions. n 3/12/2021 E. g. Intel 8085 provides data transfer between: n Register-to-register n Register-to-memory n Memory-to-register n Stack operation. Prepared by: Dr Masri Ayob 37

Arithmetic n Add, Subtract, Multiply, Divide n n Signed Integer Floating point ? May include n n n 3/12/2021 E. g. ADD C Add the content of register C to the content of accumulator A. Increment (a++) Decrement (a--) Negate (-a) Prepared by: Dr Masri Ayob 38

Shift and Rotate Operations 3/12/2021 Prepared by: Dr Masri Ayob 39

Logical n n n 3/12/2021 Bitwise operations AND, OR, NOT Example: ANA B A= A AND B Prepared by: Dr Masri Ayob 40

Conversion n 3/12/2021 E. g. Binary to Decimal Prepared by: Dr Masri Ayob 41

Input/Output n May be specific instructions n n n 3/12/2021 E. g. IN 12 Read input data from port location 12 May be done using data movement instructions (memory mapped) May be done by a separate controller (DMA) Prepared by: Dr Masri Ayob 42

Systems Control n n Privileged instructions CPU needs to be in specific state n n n 3/12/2021 Ring 0 on 80386+ Kernel mode For operating systems use Prepared by: Dr Masri Ayob 43

Program Control Instructions n Branch/Jump n n Skip n n n E. g. CALL sum Return from subroutine n 3/12/2021 e. g. increment and skip if zero n ISZ Register 1 Branch xxxx Subroutine call n n e. g. branch to x if result is zero n JZ E. g. RET Prepared by: Dr Masri Ayob 44

Nested Procedure Calls 3/12/2021 Prepared by: Dr Masri Ayob 45

Use of Stack 3/12/2021 Prepared by: Dr Masri Ayob 46

The Pentium 4’s primary registers. 3/12/2021 Prepared by: Dr Masri Ayob 47

The Pentium 4 Instruction Formats The Pentium 4 instruction formats. 3/12/2021 Prepared by: Dr Masri Ayob 48

Example of 8051 Instructions 3/12/2021 Prepared by: Dr Masri Ayob More…… 49

Thank you Q&A 3/12/2021 Prepared by: Dr Masri Ayob 50