Timing Closure Today Design Entry Synthesis Timing Place

Timing Closure Today Design Entry Synthesis Timing Place Timing Route Timing Hangzhou, April 2002 Lou Scheffer 1

Timing Analysis Give accurate time values on each pin/port of the network n Has to deal with design changes in optimization toolbox n Static Timing Analysis n u Simulation far too slow in optimization environment u Accuracy is more than enough Hangzhou Lou Scheffer II-2

Timing Analysis Requirements n Choose combination of timing analyzer and delay calculator which are appropriate for level of design u give the best accuracy u for performance that can be tolerated n Timing Analysis / Delay calculation must be able to cope with logic design changes u Incremental u Highest performance possible u Non-linear delay models Hangzhou Lou Scheffer II-3

Timing Analysis Requirements n Must handle… u Difference between rising and falling delays u Delay dependent on slew rate u Slew and delay dependent on output load u Non-linear delay equations Hangzhou Lou Scheffer II-4

Late Mode Analysis Definitions a b n n n y c x Constraints: assertions at the boundaries – Arrival times: ATa, ATb – Required arrival time: RATx Delay from a to x is the longest time it takes to propagate a signal from a to x Slack is required arrival time - arrival time. Hangzhou Lou Scheffer II-5

Example a b Hangzhou y 1 c Lou Scheffer 1 x II-6

Early mode analysis n n Definitions change as follows – longest becomes shortest – slack = arrival – required Not as important since early violations are easier to fix a b Hangzhou y 1 c Lou Scheffer 1 x II-7

Delay modeling a d x b cl Propagation Arcs Timing Model Hangzhou o Lou Scheffer Test Arc II-8