THREEDIMENSIONAL INTEGRATED CIRCUITS As Integrated circuits become more

THREE-DIMENSIONAL INTEGRATED CIRCUITS As Integrated circuits become more and more miniaturized, the only direction to go may be … up! Raymond Do Rory Nordeen Ryan Tomita

OVERVIEW Background • Why 3 -D? • Traditional Integrated Circuit methods, Emergence of 3 -D Manufacturing • Major Methods Benefits • What’s so great about 3 -Dimensions? Drawbacks and Challenges • Why don’t we see these everywhere?

WHY 3 -D? Comparing semiconductor manufacturing process nodes with some microscopic objects

TRADITIONAL METHODS • Highly Pure silicon Wafer substrate • Many individual circuits are laid up on a Silicon wafer substrate • Transistors are formed directly in the substrate, interconnected with wires, and overlaid with dielectric. • Wafer is diced to separate the individual ICs (Dies)

METHODS FOR 3 -D Four Major methods used • Monolithic • Simplest, most limited • Wafer-on-Wafer • More complicated integration using multiple wafers • Die-on-Wafer • Individual dice are stacked on a single wafer • Die-on-Die • Similar to Die-on-Wafer: paired dice are stacked

MONOLITHIC • Method researched at Stanford University • Components and connections are made in layers on a single wafer • Simplicity: no alignment or inter-layer connection issues • Limited complexity! Transistor creation processes damage any existing wiring

WAFER-ON-WAFER • 3 -D “layers” laid up on independent wafers • Wafers aligned, stacked & adhered to each other • Vertical interconnection made with “through silicon vias” • Reduced yields since one failed device in an individual chip fails entire chip

DIE-ON-WAFER & DIE-ON-DIE Die-on-Wafer Die-on-Die • Same as Wafer-on-Wafer, only one Wafer is diced prior to stacking • Individual Dice are stacked and bonded • Additional dice can be added to the stack • Even more Improved yields since all dice can be tested • Improved yields since individual dies can be tested

BENEFITS Footprint Cost Heterogeneous integration Shorter interconnects Power consumption Security Bandwidth

Footprint • Stack components in layers on top of each other Cost • Each layer can be designed, tested, and manufactured independently Bandwidth • Interconnects between layers can be wider buses than 2 D interconnects

HETEROGENEOUS INTEGRATION Heterogeneous layers • Layers can have specific functions Package size • Bottom layer keeps original thickness • Layers above bottom can be thinned • Not much thicker than a single wafer

SECURITY Sensitive circuits may be divided among layers Delayering • Circuitry can be hidden between layers • Delayering would destroy circuitry Voltage Imaging • Substrates and bonding material would blur and attenuate image Manufacturing security • Components can be spread across different layers • Layers can be manufactured at different plants

POWER CONSUMPTION Important with devices becoming mobile and distributed Shorter interconnects Potentially keep more signals on-chip • Don’t have to drive I/O

CHALLENGES

YIELD • Manufacturers need to know how 3 D IC will impact yield percentages. • Extra manufacturing step adds risks for defects. • Standard factors that affect yield include: • Die area • Circuit Density • Maturity of Process • Specific factors that affect 3 D yield include: • Extra Processing • Contamination • Alignment • Edge Effects • Design

HEAT • Average distance between system components is reduced: Good for performance but bad for dissipating heat. • Electrical proximity correlates with thermal proximity. • Heat building up within the stack must be dissipated, but how? • A team from IBM, École Polytechnique Fédérale de Lausanne (EPFL) and the Swiss Federal Institute of Technology Zurich (ETH) is working on the issue. • Microchannels with cooling systems using nanosurfaces that pipe coolants

DESIGN COMPLEXITY • 3 D integration requires sophisticated design techniques and new CAD tools. • Full utilization of wafer-thinning and throughsilicon-vias (TSV) cannot be modeled with current 2 D software. • No major companies are offering tools. • Progress is cost-driven.

TSV-INTRODUCED OVERHEAD • A typical size of TSV is much larger compared to global wires (1 to 10 μm). • TSVs take room and increase total chip area. • TSVs act as obstacles. • While the usage of TSVs is generally expected to reduce wire length, this depends on the number of TSVs and their characteristics. • TSVs also increase manufacturing cost.

TESTING • Insufficient understanding of 3 D testing issues. • To achieve high overall yield and reduce costs, separate testing of independent dies is essential. • There are serious obstacles to pre-bond testing of wafers in 3 D integration. • Wafer probing is a major limitation for thinned wafers and pre-bond wafers • Any given layer in a stacked 3 D IC does not always include complete functionality. • Methods to test for heat. • Costly test practices.

LACK OF STANDARDS • There are few standards for TSV-based 3 D-IC design, manufacturing, and packaging. • Cost-effective high-volume manufacturing will be difficult to achieve unless manufacturing standards are developed. • SEMI formed a Three-Dimensional Stacked Integrated Circuits Standards Committee. • Bonded Wafer Pair (BWP) Task Force • Inspection and Metrology Task Force • Thin Wafer Carrier Task Force

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