The Xilinx Spartan 3 FPGA EGRE 631 2209

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The Xilinx Spartan 3 FPGA EGRE 631 2/2/09

The Xilinx Spartan 3 FPGA EGRE 631 2/2/09

Basic types of FPGA’s • One time programmable • Reprogrammable (non-volatile) – Retains program

Basic types of FPGA’s • One time programmable • Reprogrammable (non-volatile) – Retains program when powered down • SRAM-based reprogramable – Must be reprogrammed each time powered up – This is usually accomplished by using a small serial PROM. – The Nexys 2 board contains a Xilinx Spartan 3 E FPGA

Spartan-3 E Architecture Fundamental Elements • Configurable Logic Blocks (CLBs) – Consists of RAM

Spartan-3 E Architecture Fundamental Elements • Configurable Logic Blocks (CLBs) – Consists of RAM based look up table to implement logic and storage elements that can be used as flip-flops or latches. • Input Output Blocks (IOBs) – Controls the flow of data between IO pins and internal logic. Supports many different signal standards. (Tristate, bidirectional, LVTTL, etc. • Block RAM (BRAM) • 18 bit Multiplier Blocks • Digital Clock Manager (DCM)

CLB’s

CLB’s

Spartan 3 Configurable Logic Blocks (CLB’s) • CLBs contain Ram based lookup tables to

Spartan 3 Configurable Logic Blocks (CLB’s) • CLBs contain Ram based lookup tables to implement logic and storage elements that can be used as flip-flops or latches. • CLBs can be programmed to perform a wide variety of logic functions as well as store data.

Spartan 3 E IO Blocks (IOB’s) • IOB’s control flow of data between IO

Spartan 3 E IO Blocks (IOB’s) • IOB’s control flow of data between IO pins and the internal logic. • Each IOB supports bidirectional data flow, 3 -state operation, and numerous different signal standards. (We will typically use LVTTL). See data sheet.

• Very low cost, high-performance logic solution for high-volume, consumer-oriented applications • Multi-voltage,

• Very low cost, high-performance logic solution for high-volume, consumer-oriented applications • Multi-voltage, multi-standard Select. IO™ interface pins - Up to 376 I/O pins or 156 differential signal pairs - LVCMOS, LVTTL, HSTL, and SSTL single-ended signal standards - 3. 3 V, 2. 5 V, 1. 8 V, 1. 5 V, and 1. 2 V signaling

I/O block

I/O block

I/O block continued

I/O block continued

CLB’s – four slices per CLB

CLB’s – four slices per CLB

Top slice of CLB

Top slice of CLB

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