The Xilinx 95108 CPLD Lecture 4 2 XC

The Xilinx 95108 CPLD Lecture 4. 2

XC 9500 CPLDs 3 JTAG Controller JTAG Port In-System Programming Controller • Function Block 1 • • Function Block 2 • I/O I/O Blocks I/O Global Clocks Global Set/Reset Global Tri-States Fast. CONNECT Switch Matrix Function Block 3 3 1 2 or 4 • • Function Block 4 5 volt in-system programmable (ISP) CPLDs 5 ns pin-to-pin 36 to 288 macrocells (6400 gates) Industry’s best pinlocking architecture 10, 000 program/erase cycles Complete IEEE 1149. 1 JTAG capability

XC 9500 Function Block Global Clocks AND Array 3 Global Tri-State 2 or 4 Macrocell 1 I/O Macrocell 18 I/O Product. Term Allocator 36 From Fast. CONNECT To Fast. CONNECT Each function block is like a 36 V 18 !

XC 9500 Product Family 9536 9572 95108 95144 95216 95288 Macrocells 36 72 108 144 216 288 Usable Gates 800 1600 2400 3200 4800 6400 t. PD (ns) 5 7. 5 10 10 Registers 36 72 108 144 216 288 Max I/O 34 72 108 133 166 192 PC 84 TQ 100 PQ 160 PQ 100 PQ 160 Packages VQ 44 PC 84 TQ 100 PQ 160 HQ 208 BG 352

Xilinx 95108 • 6 function blocks – Each contains 18 macro cells – Each macro cell behaves like a GAL 32 V 18 • AND-OR array for sum-of-products • 32 inputs and 18 outputs

Architecture of the Xilinx XC 95108 CPLD

PLDT-3 Buttons Xilinx XC 95108 CPLD 7 segment display Switches LEDs

PLDT-3 • • 12 macro cells connected to I/O pins 4 pushbuttons 8 toggle switches 8 dip switches 16 LEDs 2 7 -segment displays On-board clock signals (4 MHz and 1 Hz)

Designing a Digital Circuit

ABEL Advanced Boolean Expression Language An Example

ABEL The source file gates. abl