The Processor Lecture 3 2 Building a Datapath

The Processor Lecture 3. 2: Building a Datapath with Control 1

Learning Objectives q Describe what happens in fetching an instruction q Describe what happens in decoding an instruction q Describe the execution of following instructions q l R-type instructions l Load/store instructions l Branch and jump instructions Explain the purposes of various control signals 2

Coverage q Chapter 4. 3: Building a Datapath q Chapter 4. 4, Page 259 -264: Adding Control 3

q Building a Datapath l Chapter 4. 3 4

Fetching Instructions q Fetching instructions involves l l reading the instruction from the Instruction Memory updating the PC value to be the address of the next (sequential) instruction Add clock 4 Fetch PC = PC+4 Exec l Decode Instruction Memory PC Read Instruction Address PC is updated every clock cycle, so it does not need an explicit write control signal 5

Decoding Instructions q Decoding instructions involves l sending the fetched instruction’s opcode field bits to the control unit Fetch PC = PC+4 Exec Control Unit Decode Instruction Read Addr 1 Read Register Read Addr 2 Data 1 File Write Addr Read Write Data l Data 2 reading two values from the Register File - Register File addresses are contained in the instruction - [b 25. . b 21] and [b 20. . b 16] 6

Executing R Format Operations q R format operations (add, sub, slt, and, or) 31 R-type: l l 25 op 20 rs 15 rt 10 rd shamt 5 0 funct perform operation (op and funct) on values in rs and rt store the result back into the Register File (into location rd) Reg. Write Fetch PC = PC+4 Exec Decode Instruction Read Addr 1 Register Read Addr 2 Data 1 File Write Addr Read Write Data q Note ALU control ALU overflow zero Data 2 that Register File is not written every cycle (e. g. , sw), so we need an explicit write control signal for the Register File 7

Executing Store Operations q Store operations involve l l compute memory address by adding the base register (read from the Register File during decode) to the 16 -bit signed-extended offset field in the instruction store value (read from the Register File during decode) written to the Data Memory ALU control Instruction overflow zero Read Addr 1 Read Register Read Addr 2 Data 1 File Write Addr Read Write Data 16 Address ALU Data Memory Read Data Write Data 2 Sign Extend Mem. Write 32 8

Executing Load Operations q Load operations involve l l compute memory address by adding the base register (read from the Register File during decode) to the 16 -bit signed-extended offset field in the instruction load value (read from the Data Memory) written to the Register File Reg. Write Instruction ALU control overflow zero Read Addr 1 Read Register Read Addr 2 Data 1 File Write Addr Read Write Data 16 Address ALU Write Data 2 Sign Extend Data Memory Read Data Mem. Read 32 9

Executing Branch Operations q Branch operations involve l l compare the operands read from the Register File during decode for equality (zero ALU output) compute the branch target address by adding the updated PC to the 16 -bit signed-extended offset field in the instr Add 4 Add Shift left 2 Branch target address ALU control PC Instruction Read Addr 1 Register Read Addr 2 Data 1 File Write Addr Read Write Data 16 zero (to branch control logic) ALU Data 2 Sign Extend 32 10

Executing Jump Operations q Jump operation involves l replace the lower 28 bits of the PC with the lower 26 bits of the fetched instruction shifted left by 2 bits Add 4 4 Instruction Memory PC Read Address Instruction Shift left 2 Jump address 28 26 11

Creating a Single Datapath from the Parts q Assemble the datapath segments and add control lines and multiplexors as needed q Single cycle design – fetch, decode and execute each instruction in one clock cycle q l no datapath resource can be used more than once per instruction, so some must be duplicated (e. g. , separate Instruction Memory and Data Memory, several adders) l multiplexors needed at the input of shared elements with control lines to do the selection l write signals to control writing to the Register File and Data Memory Cycle time is determined by the length of the longest path 12

Fetch, Register, and Memory Access Portions Add Reg. Write ALUSrc ALU control 4 Instruction Memory PC Read Address Instruction l Address ALU Data Memory Read Data Write Data 2 Sign Extend 16 Memto. Reg ovf zero Read Addr 1 Register Read Addr 2 Data 1 File Write Addr Read Write Data Mem. Write Mem. Read 32 zero flag of ALU - ‘ 1’: result is zero - ‘ 0’: result is not zero 13

Full Datapath (without Jump) 14

q Adding Control Units l Chapter 4. 4, page 259 15

Adding the Control q Selecting the operations to perform (ALU, Register File and Memory read/write) q Controlling the flow of data (multiplexor inputs) 31 q Observations l l op field always in bits 31 -26 R-type: op 31 I-Type: op 25 20 15 rt rd rs 25 20 rs 31 25 addr. of registers J-type: op to be read are always specified by the rs field (bits 25 -21) and rt field (bits 20 -16) 10 5 0 shamt funct 15 rt 0 address offset 0 target address - in lw and sw rs is the base register l addr. of register to be written is in one of two places – in rt (bits 20 -16) for lw; in rd (bits 15 -11) for R-type instructions l offset for beq, lw, and sw always in bits 15 -0 16

The Main Control Unit q Control signals derived from instruction R-type Load/ Store Branch 0 rs rt rd shamt funct 31: 26 25: 21 20: 16 15: 11 10: 6 5: 0 35 or 43 rs rt 31: 26 25: 21 20: 16 4 rs rt 31: 26 25: 21 20: 16 opcode always read address 15: 0 write for R -type and load sign-extend 17

Single Cycle Datapath with Control Unit (w/o jump) 0 Add ALUOp Reg. Dst PC Read Address Instr[31 -0] Mem. Read Memto. Reg Mem. Write ALUSrc Reg. Write ovf Instr[25 -21] Read Addr 1 Register Read Instr[20 -16] Read Addr 2 Data 1 File 0 Write Addr Read 1 Instr[15 -11] Instr[15 -0] 1 PCSrc Branch Instr[31 -26] Control Unit Instruction Memory Add Shift left 2 4 Write Data zero 0 ALU Data 2 Sign 16 Extend Address Data Memory Read Data 1 Write Data 0 1 32 ALU control Instr[5 -0] 18

Single Cycle Datapath with Control Unit Instr[25 -0] 26 Shift left 2 28 1 32 0 PC+4 [31 -28] 0 Add ALUOp Instr[31 -26] Control Unit Reg. Dst Instruction Memory PC Read Address Instr[31 -0] Branch Jump 1 PCSrc Mem. Read Memto. Reg Mem. Write ALUSrc Reg. Write ovf Instr[25 -21] Read Addr 1 Register Read Instr[20 -16] Read Addr 2 Data 1 0 File Write Addr Read 1 Data 2 Instr[15 Write Data -11] Instr[15 -0] Add Shift left 2 4 Sign 16 Extend zero 0 ALU Address Data Memory Read Data 1 Write Data 0 1 32 ALU control Instr[5 -0] 19

ALU Control q ALU used for l l l Load/Store: Function = add Branch: Function = subtract R-type: Function depends on funct field ALU control (output) Function 0000 AND 0001 OR 0010 add 0110 subtract 0111 set-on-less-than 20

ALU Control q Assume 2 -bit ALUOp derived from opcode l opcode Combinational logic derives ALU control ALUOp Operation funct ALU function ALU control lw 00 load word XXXXXX add 0010 sw 00 store word XXXXXX add 0010 beq 01 branch equal XXXXXX subtract 0110 R-type 10 add 100000 add 0010 subtract 100010 subtract 0110 AND 100100 AND 0000 OR 100101 OR 0001 set-on-less-than 101010 set-on-less-than 0111 21