The Memory Hierarchy Topics n n n Storage

The Memory Hierarchy Topics n n n Storage technologies and trends Locality of reference Caching in the memory hierarchy

Random-Access Memory (RAM) Key features n RAM is packaged as a chip. Basic storage unit is a cell (one bit per cell). n Multiple RAM chips form a memory. n Static RAM (SRAM) n n Each cell stores bit with a six-transistor circuit. Retains value indefinitely, as long as it is kept powered. Relatively insensitive to disturbances such as electrical noise. Faster and more expensive than DRAM. Dynamic RAM (DRAM) n n Each cell stores bit with a capacitor and transistor. Value must be refreshed every 10 -100 ms. Sensitive to disturbances. Slower and cheaper than SRAM.

SRAM vs DRAM Summary Tran. per bit Access time Persist? Sensitive? Relative Cost Applications SRAM 6 1 X Yes No 100 x cache memories DRAM 1 10 X No Yes 1 X Main memories, frame buffers

Conventional DRAM Organization d x w DRAM: n d x w DRAM d supercells, w bits/cell dw total bits 16 x 8 DRAM chip 0 2 bits / 2 3 0 addr (to CPU) 1 cols 1 rows memory controller supercell (2, 1) 2 8 bits / 3 data internal row buffer

Reading DRAM Supercell (2, 1) Select row 2 with row access strobe (RAS). Copy row 2 copied from DRAM array to row buffer. 16 x 8 DRAM chip 0 RAS = 2 1 cols 2 3 0 2 / addr 1 rows memory controller 2 8 / 3 data internal row buffer

Reading DRAM Supercell (2, 1) Select column 1 with column access strobe (CAS). Copy supercell (2, 1) from buffer to data lines, and eventually back to the CPU. 16 x 8 DRAM chip 0 CAS = 1 2 / 2 3 0 addr To CPU 1 rows memory controller supercell (2, 1) 1 cols 2 8 / 3 data supercell (2, 1) internal row buffer

8 -Byte Access With Memory Modules addr (row = i, col = j) : supercell (i, j) DRAM 0 64 MB memory module consisting of eight 8 Mx 8 DRAMs DRAM 7 bits bits 56 -63 48 -55 40 -47 32 -39 24 -31 16 -23 8 -15 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 bits 0 -7 0 64 -bit doubleword at main memory address A 64 -bit doubleword Memory controller

Enhanced DRAMs are based on a conventional DRAM core. n Fast page mode DRAM (FPM DRAM) l Access contents of row with [RAS, CAS, CAS] instead of [(RAS, CAS), (RAS, CAS)]. n Extended data out DRAM (EDO DRAM) l Enhanced FPM DRAM with more closely spaced CAS signals. n Synchronous DRAM (SDRAM) l Driven with rising clock edge instead of asynchronous control signals. n Double data-rate synchronous DRAM (DDR SDRAM) l Enhancement of SDRAM that uses both clock edges as control signals. n Video RAM (VRAM) l Like FPM DRAM, but output is produced by shifting row buffer l Dual ported (allows concurrent reads and writes)

Nonvolatile Memories DRAM and SRAM are volatile memories n Lose information if powered off. Nonvolatile memories retain value even if powered off. n n n Generic name is read-only memory (ROM). Misleading because some ROMs can be read and modified. Core memory used to implement ABC requirements. Types of ROMs n n Programmable ROM - fused (PROM) Eraseable programmable ROM - UV (EPROM) Electrically eraseable PROM – in place (EEPROM) Flash memory – portable EEPROM Firmware n Program stored in a ROM l Boot time code, BIOS (basic input/ouput system) l graphics cards, disk controllers.

The Hardware Bus

Typical Bus Structure Connecting CPU and Memory A bus is a collection of parallel wires that carry address, data, and control signals. Buses are typically shared by multiple devices. CPU chip register file ALU system bus interface I/O bridge memory bus main memory

Memory Read Transaction CPU places address A on the memory bus. register file %eax Load operation: ALU I/O bridge bus interface movl A, %eax A main memory 0 x A

Memory Read Transaction Main memory reads A from the memory bus, retrieves word x, and places it on the bus. register file %eax Load operation: ALU I/O bridge bus interface movl A, %eax x main memory 0 x A

Memory Read Transaction CPU reads word x from the bus and copies it into register %eax. register file %eax x Load operation: ALU I/O bridge bus interface movl A, %eax main memory 0 x A

Memory Write Transaction CPU places address A on bus. Main memory reads it and waits for the corresponding data word to arrive. register file %eax y Store operation: ALU I/O bridge bus interface movl %eax, A A main memory 0 A

Memory Write Transaction CPU places data word y on the bus. register file %eax y Store operation: ALU I/O bridge bus interface movl %eax, A y main memory 0 A

Memory Write Transaction Main memory reads data word y from the bus and stores it at address A. register file %eax y Store operation: ALU I/O bridge bus interface movl %eax, A main memory 0 y A

The Hardware Disk

Disk Geometry Disks consist of platters, each with two surfaces. Each surface consists of concentric rings called tracks. Each track consists of sectors separated by gaps. tracks surface track k spindle sectors gaps

Disk Geometry (Multiple-Platter View) Aligned tracks form a cylinder k surface 0 platter 0 surface 1 surface 2 platter 1 surface 3 surface 4 platter 2 surface 5 spindle

Disk Capacity: maximum number of bits that can be stored. n Capacity in gigabytes (GB), 1 GB = 10^9 bytes. Capacity is determined by: n n n Recording density (bits/inch): number of bits that can be squeezed into a 1 inch segment of a track. Track density (tracks/inch): number of tracks that can be squeezed into a 1 inch radial segment. Areal density (bits/inch 2): recording x track density

Computing Disk Capacity = bytes/sector x sectors/track x tracks/surface x surfaces/platter x platters/disk = bytes/disk Example: n n n 512 bytes/sector 300 sectors/track 20, 000 tracks/surface 2 surfaces/platter 5 platters/disk Capacity = 512 x 300 x 20000 x 2 x 5 = 30, 720, 000 = 30. 72 GB

Disk Operation (R-rated Demo) The disk surface spins at a fixed rotational rate The read/write head is attached to the end of the arm and flies over the disk surface on a thin cushion of air. spindle By moving radially, the arm can position the read/write head over any track.

Disk Operation (Multi-Platter View) read/write heads move in unison from cylinder to cylinder arm spindle

Disk Access Time Average time to access a sector: n Taccess = Tavg seek + Tavg rotation + Tavg transfer Seek time (Tavg seek) n n Time to position heads over target cylinder. Typical Tavg seek = 9 ms Rotational latency (Tavg rotation) n n Time for first bit of target sector to pass under r/w head. Typical Tavg rotation = 4 ms Transfer time (Tavg transfer) n n Time to read the bits in the target sector. Typical Tavg transfer =. 02 ms

Typical Disk Access Times Values: n Tavg seek = 9 ms n Tavg Rotation = 4 ms Tavg Transfer =. 02 ms Total access = 9 + 4 +. 02 = 13. 02 ms n n Important points: n n n Access time dominated by seek time and rotational latency. First bit in a sector is the most expensive, the rest are free. SRAM access time is about 4 ns/doubleword, DRAM about 60 ns l Disk is about 40, 000 times slower than SRAM, l Disk is about 2, 500 times slower then DRAM.

Logical Disk Blocks Modern disks present a simpler abstract view of the complex sector geometry: n The set of available sectors is modeled as a sequence of logical blocks (0, 1, 2, . . . ) Mapping between logical blocks and physical sectors n n Maintained by hardware/firmware device called disk controller. Converts requests for logical blocks into (surface, track, sector) triples. Allows controller to set aside spare cylinders. n Accounts for the difference in “formatted capacity” and “maximum capacity”.

I/O Bus CPU chip register file ALU system bus memory bus main memory I/O bridge bus interface I/O bus USB controller mouse keyboard graphics adapter disk controller monitor disk Expansion slots for other devices such as network adapters.

Reading a Disk Sector CPU chip register file ALU CPU initiates a disk read by writing a command, logical block number, and destination memory address to a port (address) associated with disk controller. main memory bus interface I/O bus USB controller mouse keyboard graphics adapter disk controller monitor disk

Reading a Disk Sector CPU chip register file ALU Disk controller reads the sector and performs a direct memory access (DMA) transfer into main memory bus interface I/O bus USB controller mouse keyboard graphics adapter disk controller monitor disk

Reading a Disk Sector CPU chip register file ALU When the DMA transfer completes, the disk controller notifies the CPU with an interrupt (i. e. , asserts a special “interrupt” pin on the CPU) main memory bus interface I/O bus USB controller mouse keyboard graphics adapter disk controller monitor disk

Locality

Storage Trends Ratio 2000: 1980 represents improvement (bigger is better) SRAM Disk metric 1980 1985 1990 1995 2000: 1980 $/MB access (ns) 19, 200 300 2, 900 150 320 35 256 15 100 2 190 150 metric 1980 1985 1990 1995 2000: 1980 $/MB 8, 000 access (ns) 375 typical size(MB) 0. 064 880 200 0. 256 100 4 30 70 16 1 60 64 8, 000 6 1, 000 metric 1985 1990 1995 2000: 1980 100 75 10 8 28 160 0. 30 10 1, 000 0. 05 8 9, 000 10, 000 11 9, 000 1980 $/MB 500 access (ms) 87 typical size(MB) 1 Easier to make disks & memory cheaper and larger. Harder to make disks & memory faster (10 x improvement). Culled from back issues of Byte and PC Magazine.

CPU Clock Rates processor clock rate(MHz) cycle time(ns) 1980 8080 1 1, 000 1985 286 6 166 1990 386 20 50 1995 Pent 150 6 2000 P-III 750 1. 6 n 1000/Mhz = cycle time in ns CPU: 750 x improvement n Recall Disk & memory: 10 x improvement n 2000: 1980 750

The CPU-Memory Gap n n n Increasing gap between DRAM, disk, and CPU speeds CPU drops 1000 x, DRAM drops 10 x Must do something so memory doesn’t slow us down

Locality Principle of Locality: n n n Programs tend to reuse data and instructions near those they have used recently, or that were recently referenced themselves. Temporal locality: Recently referenced items are likely to be referenced in the near future. Spatial locality: Items with nearby addresses tend to be referenced close together in time. Locality Example: sum = 0; for (i = 0; i < n; i++) sum += a[i]; return sum; • Data – Reference array elements in succession (stride-1 reference pattern): Spatial locality – Reference sum each iteration: Temporal locality • Instructions – Reference instructions in sequence: Spatial locality – Cycle through loop repeatedly: Temporal locality

Locality Example #1 Question: Does this function have good locality? int sumarrayrows(int a[M][N]) { int i, j, sum = 0; for (i = 0; i < M; i++) for (j = 0; j < N; j++) sum += a[i][j]; return sum }

Locality Example #2 Question: Does this function have good locality? int sumarraycols(int a[M][N]) { int i, j, sum = 0; for (j = 0; j < N; j++) for (i = 0; i < M; i++) sum += a[i][j]; return sum }

Locality Example #3 Question: Can you permute the loops so that the function scans the 3 -d array a[] with a stride-1 reference pattern (and thus has good spatial locality)? int sumarray 3 d(int a[M][N][N]) { int i, j, k, sum = 0; for (i = 0; i < M; i++) for (j = 0; j < N; j++) for (k = 0; k < N; k++) sum += a[k][i][j]; return sum }

Practice problem #6. 5, p. 482

Caches

Memory Hierarchies Some fundamental and enduring properties of hardware and software: n n n Fast storage technologies cost more per byte and have less capacity. The gap between CPU and main memory speed is widening. Well-written programs tend to exhibit good locality. These fundamental properties complement each other beautifully. They suggest an approach for organizing memory and storage systems known as a memory hierarchy.

Memory Hierarchy Smaller, faster, and costlier (per byte) storage devices Larger, slower, and cheaper (per byte) storage devices L 5: L 0: registers CPU registers hold words retrieved from L 1 cache. L 1: on-chip L 1 cache (SRAM) L 2: L 3: L 4: off-chip L 2 cache (SRAM) L 1 cache holds cache lines retrieved from the L 2 cache memory. L 2 cache holds cache lines retrieved from main memory (DRAM) local secondary storage (local disks) remote secondary storage (distributed file systems, Web servers) Main memory holds disk blocks retrieved from local disks. Local disks hold files retrieved from disks on remote network servers.

Caches Cache: A smaller, faster storage device that acts as a staging area for a subset of the data in a larger, slower device. Fundamental idea of a memory hierarchy: n For each k, the faster, smaller device at level k serves as a cache for the larger, slower device at level k+1. Why do memory hierarchies work? n n n Programs tend to access the data at level k more often than they access the data at level k+1. Thus, the storage at level k+1 can be slower, and thus larger and cheaper bit. Net effect: A large pool of memory that costs as much as the cheap storage near the bottom, but that serves data to programs at the rate of the fast storage near the top.

Caching in a Memory Hierarchy Level k: 8 4 9 10 4 Level k+1: 14 10 3 Smaller, faster, more expensive device at level k caches a subset of the blocks from level k+1 Data is copied between levels in block-sized transfer units. Caching is done by columns. Other organizations are possible. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Larger, slower, cheaper storage device at level k+1 is partitioned into blocks.

General Caching (Animation) 14 12 7 Level k: n 0 1 2 3 12 4* 9 14 3 7 Request 12 7 n 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Program finds block in cache Cache miss n 12 4 7 Level k+1: Cache hit Request 7 12 14 Block not in cache, must fetch from next level If level k cache is full, then some current block must be replaced (evicted). Which one is the “victim”? l Placement policy: where can the new block go? e. g. , b mod 4 l Replacement policy: which block should be evicted? e. g. , LRU

General Caching Concepts Types of cache misses: n Cold (compulsary) miss l Cold misses occur because the cache is empty. n Conflict miss l Conflict misses occur when the level k cache is large enough, but multiple data objects all map to the same level k block. l E. g. Referencing blocks 0, 8, . . . would miss every time. n Capacity miss l Occurs when the set of active cache blocks (working set) is larger than the cache. l E. g. Referencing blocks 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7

Examples of Caching in the Hierarchy Cache Type What Cached Where Cached Registers 4 -byte word CPU registers 0 Compiler Address translations L 1 cache 32 -byte block L 2 cache 32 -byte block Virtual Memory 4 -KB page On-Chip TLB 0 Hardware On-Chip L 1 Off-Chip L 2 Main memory Buffer cache Main memory 1 Hardware 100 Hardware+ OS 100 OS TLB Parts of files Network buffer Parts of files cache Browser cache Web pages Local disk Web cache Remote server disks Web pages Local disk Latency (cycles) Managed By 10, 000 AFS/NFS client 10, 000 Web browser 1, 000, 000 Web proxy server