The MCC testing environment MCC FDR 10 October

The MCC testing environment MCC FDR 10 October 2002 P. Morettini 10/10/02 1

Introduction Since the beginning of the MCC development it was clear that it was impossible to test all its functionalities using a pixel detector module. The typical rates one can obtain at a test beam or with a source are far from the design ones. Moreover, being impossible to control the input, its difficult to perform a detailed test of the chip response. For this reason we developed a test strategy based on a software program (Sim. Pix) being able to generate arbitrary input to the MCC and a set of hardware tools to send the input pattern to the MCC and read back the output for the analysis. MCC Verilog Model MCC P. Morettini 10/10/02 Sim. Pix Design Specification Detector Simulation 2

Sim. Pix block diagram Clock Generator MCC command generator Detector response and LVL 1 simulator FE behavioral simulation MCC input preparation MCC output decoding MCC or Verilog model Time oriented database Automatic analysis P. Morettini 10/10/02 3

Sim. Pix implementation Sim. Pix is a C++ program running under Windows. It uses TCL/TK for the GUI. It’s easily portable to Unix/Linux. Thanks to the Object Oriented design it’s highly modular and flexible. It’s easy to add new components or to replicate existing ones (we are considering to use it to study the Pixel ROD performance, and this will require the addition of a ROD simulation and the replication of the MCC and FE simulator). The modular design extends inside the different components; so, for example, it’s possible to test two different implementation of the MCC event builder leaving the rest of the MCC model untouched. P. Morettini 10/10/02 4

Sim. Pix functions Pure simulation tool: the full Pixel DAQ chain is simulated to evaluate bottlenecks and inefficiencies. • Architecture robustness studies • DAQ impact on detector performance Design validation: the software simulation is compared with the output of the Verilog model. • Implementation validation • Verilog code debugging Chip test: the software simulation is compared with the output of a true MCC • Post-production tests • Debugging of anomalies P. Morettini 10/10/02 5

Standard Sim. Pix operations Module selector Geant Module Hits Random Hits/Noise Generator C++ FE Model MCC Automatic Comparison C++ MCC Model In the standard configuration Sim. Pix compares the output of a true MCC or of a Verilog model with the output of a behavioral C++ MCC model. The input is taken from a Geant simulation and modified by a C++ FE model. P. Morettini 10/10/02 6

Sim. Pix as a simulation tool Module selector Geant Module Hits Random Hits/Noise Generator C++ FE Model MCC Automatic Comparison C++ MCC Model In pure simulation mode no external MCC is connected. The Noise Generator can be used to investigate the response of the system as a function of the occupancy of the pixel detector. P. Morettini 10/10/02 7

Sim. Pix as a simulation tool Module Selector Geant Module Hits Random Hits/Noise Generator C++ FE Model MCC Automatic Comparison C++ MCC Model Geant Ntuple In general the Module Selector chooses one single module for the simulation. It can, however, loop over the entire Pixel Detector. In this case it is possible to save the output in the same format as the input simulation, to check the impact of the electronic chain on the physics performance of the detector. P. Morettini 10/10/02 8

The Sim. Pix scripting language To simplify the writing of the MCC test vectors we implemented inside Sim. Pix a scripting language. The language provides: • Support for all the MCC commands • Generation of Fe hits and Eo. E • Timing control on the DCI and DTI lines • Variable substitutions • Elementary flow control (loops) P. Morettini 10/10/02 9

The Sim. Pix scripting language Module selector Geant Module Hits C++ FE Model MCC Random Hits/Noise Generator Automatic Comparison Script Interpreter C++ MCC Model Script File In script mode, the FE model is bypassed, and the FE output is generated directly by the interpreter. P. Morettini 10/10/02 10

Output verification in script mode The script commands TRIGGER 10 EVENT HITS_EOE ffff 3 1 END_EVENT Delay FE mask Number of hits (mean and sigma) generate a TRIGGER command to the MCC and, after 10 clock cycles, a set of hits + Eo. E in all the FE (3 hits in average, with a spread of one hit). The hits will be generated randomly, and the analysis module will check the presence of the generated hits in both the MCC outputs. P. Morettini 10/10/02 11

Support for FE and MCC configuration commands The control and configuration lines (CCK, LD, DI, STRO) are usually ignored by Sim. Pix; in script mode however the MCC model provides the expected duration of CCK, LD, RSOb and STRO depending on the command issued and on the MCC register settings. The expected durations are then compared with the actual chip output. The expected output of the MCC inspection commands (RD_REGISTER, RD_FIFO) can be specified in the script to allow automatic checking: WR_REGISTER FEEN 0 xfaff RD_REGISTER FEEN 0 xfaff P. Morettini 10/10/02 Read register FEEN; the expected output is faff plus the header 12

Interface with the MCC Verilog Model In order to check the MCC Verilog Model before submission we have interfaced it with Sim. Pix. The interface consists of a TCP connection between the PC running Sim. Pix and the workstation running the Verilog simulation. In this way we avoid an excessive load of a single CPU and we do not force Sim. Pix to run on the same architecture as Verilog. Sim. Pix activates the Verilog simulator on the remote machine, and opens the TCP connection. At every clock cycle it sends DCI, LVL 1 and the 16 serial FE outputs. The Verilog model replies with DTO, DTO 2, LD, CCK, DI. The two simulations run in parallel on the two machines. P. Morettini 10/10/02 13

Tests of the MCC-DSM Verilog model The MCC-DSM Verilog behavioral model has been tested extensively with a set of test vectors generated with the Sim. Pix scripting language. The C++ MCC-DSM model included in Sim. Pix has been tuned to reproduce the Verilog model behavior in a reliable way. The Sim. Pix automatic analysis module is used to compare the Verilog model output with the output of the behavioral C++ simulation. Some of the vectors have been run also on the netlist. This type of run is very CPU demanding. P. Morettini 10/10/02 14

Verilog code validation with Sim. Pix Module selector Geant Module Hits C++ FE Model Verilog Model Random Hits/Noise Generator Automatic Comparison Script Interpreter C++ MCC Model Script File The output of the Verilog model and of the C++ model are compared by the automatic analysis tool. At the beginning some adjustment is needed to equalize the detailed timing of the two models (and some small difference remains). P. Morettini 10/10/02 15

MCC-DSM Test Vectors (I) 1 - Read and Write operations on registers and FIFOs: • Global. Reset command test; • read and write operations on Receivers' FIFOs and Pending. Level 1 FIFO; • read and write operations on configuration registers. 2 - Output line test: • 1010. . . pattern output by setting CSR-OPAT. 3 - Front-End configuration: • read and write operations using Write. FE and Read. FE; • single Front-End selection; • Front-End reset command. 4 - Receiver test: • write operations using Write. Receiver; • event reconstruction in Event. Playback mode; • single Front-End selection. P. Morettini 10/10/02 16

MCC-DSM Test Vectors (II) 5 - Full event reconstruction: • 40, 80, 160 Mbit/s output modes test; • TOT selection; • single Front-End selection; • Event. Counter. Reset and Bunch. Counter. Reset. 6 - Flag production: • • different LVL 1 numbers in one Receiver; different LVL 1 numbers among 16 Receivers; Receiver warning: Receivers' FIFOs overflow; FE warning. 7 - LVL 1 issues: • L 1 ID and BCID counters test; • consecutive LVL 1 and L 1 ID and BCID test; • skipped LEVEL 1 counter test. P. Morettini 10/10/02 17

An example: receiver overflow //////////////////////////// // Variables definitions //////////////////////////// Tr = 7 // Delay after Trigger commands TRAIL 50000 //////////////////////////// // MCC initialization //////////////////////////// 100 SOFT_RESET 30 WR_REGISTER CSR 1 c 30 WR_REGISTER FEEN ffff … //////////////////////////// // Test #2 - hit overflow on Receiver number 1, 3, 5, 7, 9, 11, 13 and 15 //////////////////////////// 50000 ENABLE_DATATAKE LOOP i 1 15 250 TRIGGER $Tr EVENT HITS_EOE aaaa 40 4 HITS_EOE 5555 3 1 END_EVENT END_LOOP 40 Mbit/s with To. T 40± 4 Hits/Event in 8 FEs P. Morettini 10/10/02 18

C++ MCC LVL 1 Hits LVL 1 FE out Anomalies P. Morettini 10/10/02 C++ MCC out 19

Example 2: different output speeds //////////////////////////// // Test #3 - 80 Mbit/s (same data on both links) test //////////////////////////// 15000 SOFT_RESET 30 WR_REGISTER CSR 001 e // 80 Mbit/s (same data on both links) 30 WR_REGISTER FEEN ffff // All FE enabled 30 WR_REGISTER LV 1 0000 // No contiguous LEVEL 1 10 ENABLE_DATATAKE LOOP i 1 $N 2 200 TRIGGER 25 EVENT ffff 3 3 END_LOOP //////////////////////////// // Test #4 - 160 Mbit/s (80 Mbit/s on each link) test //////////////////////////// 20000 SOFT_RESET 30 WR_REGISTER CSR 001 f // 160 Mbit/s (80 Mbit/s on each link) 30 WR_REGISTER FEEN ffff // All FE enabled 30 WR_REGISTER LV 1 0000 // No contiguous LEVEL 1 10 ENABLE_DATATAKE LOOP i 1 $N 2 100 TRIGGER 25 EVENT ffff 3 3 END_LOOP P. Morettini 10/10/02 20

40 Mb/s P. Morettini 80 Mb/s 2 lines 10/10/02 80 Mb/s 1 line 160 Mb/s 40 Mb/s No To. T 21

MCC-DSM test in the lab Module Selector Geant Module Hits C++ FE Model MCCex Random Hits/Noise Generator Automatic Comparison Script Interpreter C++ MCC Model LSA/ Patt. Gen Script File We have two tools for testing the functionality of the MCC in the lab. The first is an “ad-hoc” VME card (MCCex), the second is a general purpose Pattern Generator/Logic State Analyzer. In both cases the input to the MCC is generated by Sim. Pix, either via a script file or from a Geant simulation. P. Morettini 10/10/02 22

The MCC Exerciser 2 x 8 Mbit Memory Card VME Interface P. Morettini 10/10/02 MCC It’s a 6 U VME card developed for testing the MCC-AMS. It provides 20 bi-directional 8 Mbit deep channels, which can be used to send inputs to the MCC or receive outputs. Data are stored in a VME accessible RAM. Pro: • Deep memory. • Fast data download/upload. Cons: • Designed for MCC-AMS; no DTO 2 and 80 Mbit/s support. • Clock fixed at 40 MHz. 23

The HP 16700 A Patt. Gen/LSA It’s a general purpose pattern generator/logic state analyzer. The connection to the MCC requires a support card with LVDS/CMOS converter. Pro: • Full clock speed and phase control • Possibility to perform test in stand-alone mode. Cons: • Only 512 Kbit deep • Slow upload/download (ASCII data over a 10 Mbit/s ethernet) P. Morettini 10/10/02 24

HP 16700 A view P. Morettini 10/10/02 25

Sim. Pix view C++ model MCC P. Morettini 10/10/02 26

Support card for the MCC-DSM To Remote MCC To HP 16700 A LVDS Conversion CMOS Conversion AMS Footprint MCCex Connection MCCex to TFM Mode P. Morettini 10/10/02 Routing and Delay Adjust MCCex to MCC-DSM Mode MCC-DSM Socket HP 16700 A to MCC-DSM Mode 27

Support card for the MCC-DSM To Remote MCC To HP 16700 A LVDS Conversion LVDS/CMOS Conversion AMS Footprint MCCex Connection MCCex to TFM Mode P. Morettini 10/10/02 Routing and Delay Adjust MCCex to MCC-DSM Mode MCC-DSM Socket HP 16700 A to MCC-DSM Mode 28

Support card for the MCC-DSM To Remote MCC To HP 16700 A LVDS Conversion CMOS Conversion AMS Footprint MCCex Connection MCCex to TFM Mode P. Morettini 10/10/02 Routing and Delay Adjust MCCex to MCC-DSM Mode MCC-DSM Socket HP 16700 A to MCC-DSM Mode 29

TFM Connection The TOM Card LSA connections MCCex Connection MCC-DSM socket P. Morettini 10/10/02 30

MCC Output Analysis Sim. Pix automatically checks the correspondence between the output pattern and the FE hits generated at the input. Moreover it checks if the MCC output is compatible with the prediction of the C++ model. It’s possible to click on any event in the Sim. Pix GUI to have it fully decoded. Once the MCC output pattern has been validated it is possible to store it in the LSA together with the input, and use it to check small volumes of dies. In the following we see few examples of the Sim. Pix analysis tools. P. Morettini 10/10/02 31