The Implementation of DeltaSigma Modulation in Digitalto Analog

The Implementation of Delta-Sigma Modulation in Digital-to. Analog Converter Group member: Zhaoxin Mamengduo Cfang Stanley 1

Project Idea Motivation: EE 505 CMOS Data Conversion circuits During the process of digital-to-analog converting � Use Delta-sigma modulator to push noise in music to high frequency band � Use speaker/headphone as the low-pass filter to filtrate high frequency white noise 2

Top Level Components Deltasigma modulation Low pass filter 3 PCM(digital) In Serial Pulse Width Modulation (PWM, digital) Signal In Serial

Level-shifter for DVD Output Signal �Output signal(from DVD) voltage: -0. 5 V~+0. 5 V Schmidt trigger: SN 74 LS 14 N rheostat 4

Demo � Film 1 Play CD http: //www. youtube. com/watch? v=582 E_OXe. VOU �Film 2 Input signal voltage shift http: //www. youtube. com/watch? v=u. Bhc. Lwn 46 Q M&feature=youtu. be �Film 3 Sleep mode http: //www. youtube. com/watch? v=Q 74 URMVuh F 8&feature=youtu. be 5

The Structure of DAC module 6

Input: PCM 7

The 3 -stage Delta-sigma Modulation PCM � Y 1＝X+(1－Z-1) • Q � Y 2＝－Q 1＋（1－Z－1) • Q 2 � Y 3＝（－Q 2）＋ (1－Z-1) • Q 3 8 � Y＝ X+（1－Z－1)3 • Q 3 PWM

Eleven PWM Signals 9

Output: PWM �PWM: digital signal but has analog info. 10

Matlab Simulation: Noise is pushed to higher frequencies 11

Using Filter to Cutoff Noise 12

One Order Noise Shaping Model �Q＝Y－U �U－Y＝－Q �U＝X－Q 13

One Order Noise Shaping Model �U(n)＝X(n)－Q(n-1) �Q(n)＝Y(n)－U(n) �Y(n)＝X(n)－Q(n－1)＋Q(n) ＝X(n)＋Q(n)－Q(n－ 1) � Q(n)－Q(n－1)＝（1－Z－1） • Q �Y＝X＋（1－Z－1） • Q 14

The 3 -stage Delta-Sigma Modulation � Y 1＝X+(1－Z-1) • Q � Y 2＝－Q 1＋（1－Z－1) • Q 2 � Y 3＝（－Q 2）＋ (1－Z-1) • Q 3 15 � Y＝ X+（1－Z－1)3 • Q 3

Clock Synchronization with DVD �Input signal(from DVD) is in serial: Need to decode SPDIF signal �So need to synchronize clock with DVD 16

Clock Synchronization and Data Extraction 17

Clock Synchronization � 44. 1 k. Hz frame rate× 2 channel × 32 data× 2 phase ＝ 5. 6448 MHz �Keep detecting : temp 1=temp 2=temp 3 & temp 4=temp 5=temp 6 �Then generate sampling clock @ center pulse 18

Clock Synchronization(cont. ) 19

Data Extraction 20

Data Extraction(cont. ) �Keep detecting frame header 11100010 or 00011101 | 11100100 or 00011011 21

Sleep Mode(Power Saving) system 22

Volume Control �Matlab verification �Lower volume: right shift �Larger volume: left shift �Debounce module( real world) 23

Reference �http: //en. wikipedia. org/wiki/Delta- sigma_modulation �http: //www. cscamm. umd. edu/programs/ocq 05/ad ams/adams_ocq 05. pdf �http: //www. beis. de/Elektronik/Delta. Sigma/Delta. Si gma. html �http: //www. intersil. com/data/an/an 9504. pdf �http: //hephaestusaudio. com/media/2009/07/MAS H-Delta-Sigma. pdf 24

Thank you! Q and A 25