The IA64 architecture and Itanium processors Explicitly Parallel

The IA-64 architecture and Itanium processors Explicitly Parallel Instruction Computing Frans Dondorp Presentation et 4 074, January 8 th 2001

Contents Introduction to the IA-64 architecture and EPIC The Itanium processor Branch removal Predication Speculative execution Control speculation Data speculation Comparison: ARM conditional instructions

Introduction to the IA-64 architecture Joint research by Intel and Hewlett-Packard (1994) exploitation of the ILP concept tight coupling of hard- and software EPIC is introduced as basic concept: Explicitly Parallel Instruction Computing This results in a more complex task for the compiler and Hardware support for communication of meta-information speculation, predication and branch hints “The future of computing” – Intel web site

The Itanium processor The Itanium , formerly code-named Merced , is the first processor based on the IA-64 architecture Still a prototype, compilers announced (as of nov. 2000) 10 -stage pipeline, running at 800 Mhz To support EPIC, it is equipped with: 4 ALU’s, 4 MMX units, 4 FPU’s (2 SP, 2 DP), 2 L/S units, 3 br units MS Win 2 K and Linux announced (as of oct. 2000)

IA 64 resources and instructions Register resources Static Stacked / Rotating Support for register stack and software pipelining 128 GR’s 128 FR’s 128 AR’s 8 BR’s r 0 r 1. . . . r 31 r 32. . . r 126 r 127 f 0 f 1. . . . f 31 f 32. . . f 126 f 127 ar 0 ar 1. . . . f 126 f 127 b 0 b 1. . b 7 82 b 64 b Rotating 64 + 1 b Deferred exception (Not A Thing, Na. T) Control speculation Function call linkage and return (64 b address space!) AR application register BR Branch register FR Floating point register GR General register PR Predicate register 64 b 64 PR’s p 0. . . p 15 p 16. . p 62 p 63 Holds result of a conditional expression evaluation Predication 1 b

IA 64 resources and instructions Instruction encoding Instruction 2 Instruction 1 Instruction 0 Template 41 b {. mii ld 8 r 1 = 4[r 2] add r 3 = r 1, r 3 shr r 7 = r 4, r 12 } {. mbb ld 8 r 6 = 8[r 5] (p 3) br. cond Label 1 (p 4) br. cond Label 2 } Templates are used to group instructions to exploit parallel execution by keeping execution units buzy. IA-64 “Bundle” 5 b Predicates are used to allow for conditional execution. 6 bits used to address 64 predicate registers Instruction format Op Reg 1 Reg 2 Reg 3 Predicate 14 b 7 b 7 b 7 b 6 b The Itanium processor issues 8 ops/clock: M ALU ALU I I M B B L/S FP S MMX MMX FP D BR BR BR

Branch removal Branch-prediction is costly Cost of misprediction is proportional to pipeline length Optimizing the use of prediction resources can significantly improve the overall performance Conditional instructions can eliminate the need for branches cmp r 1, r 2 beq equal moveq r 1, #0 movne r 2, #0 bal end. equal mov r 2, #0. end Executes only if eq-bit is set in status register; else NOP

Branch removal – Conditional instructions can reduce a branch-penalty due to a misprediction from N pipeline-stages to 1 Implementing conditional instructions in instruction space directly increases instruction-size while the amount of conditions to test on is limited (typically to a few bits in the processor status register) ARM Conditional Instructions Unbalanced execution paths: conditional code might decrease performance in favor of a branch misprediction

Branch removal – Conditional instructions Example: conditional code performance (one instruction executed each cycle) cmp r 1, r 2 moveq r 1, #0 bne end addeq r 2, #10 mov r 1, #0 ldbeq r 3, (r 5)+ inceq r 3 r 1 r 2 6 NOP’s stbeq r 3, (r 5)+ vs add r 2, #10 ldb r 3, (r 5)+ inc r 3 inceq r 1 stb r 3, (r 5)+ mov r 2, #0 inc r 1 LOSS: 6 r 1 r 2 mispredict . end mov r 2, #0 On a machine with a 5 -stage pipeline, conditional instructions would lead to performance loss The compiler should decide! Pipeline flushed: branchpenalty LOSS: #pipeline

Predication: tagging instructions with a boolean value if r 4 0 then r 1 = (r 2 + r 3) if r 4 0 then r 6 = MEM(r 5) cmp. ne (p 1) add (p 1) ld 8 p 1, p 0 = r 4, 0; ; r 1 = r 2, r 3 r 6 = [r 5] SET BOOLEAN VALUES Compare r 4 to #0; not equal p 1 is TRUE if r 4 0 p 2 = NOT(p 1) The limitations of conditional instructions are decreased by predication: with predication the amount of conditions to test on equals the number of predicate registers

Predication – moving instructions Advantages of predication The compiler has more freedom when scheduling if predicates are guaranteed not to conflict. Code Motion Upward Downward Code motion past branches and Ld/Str ops results in speculative execution

Speculative execution The compiler selects commonly executed blocks Instruction selection, prioritization and reordening To enable agressive code-motion done by the compiler, explicitly speculative instructions must be available

Speculative execution – Control speculation IA-64 provides speculative load instructions ld 8. s r 1 = [r 2] use r 1 instr. A instr. B . . . br br The load instruction is replaced by a speculative load Na. T may be written in r 1 speculation check ld 8 r 1 = [r 2] chk. s use r 1 Exception Handling: If a speculative load raises an exception, a deferred exeception token (Na. T) is written to the target register. This Na. T is propagated by almost all instructions. chk. s checks for Na. T and if present, jumps to fix-up code (compiler generated). This fix-up code may excute the load non-speculatively and return to main code afterwards.

Speculative execution – Data speculation IA-64 provides advanced load instructions The load instruction is replaced by an advanced load ld 8. a r 1 = [r 2] instr. A use r 1 . . . instr. A reg# addr size . . . reg# addr size store . . . . reg# addr size ld 8 r 1 = [r 2] chk. a reg#, addr and size are stored in the advanced load address table (ALAT) use r 1 advanced load check Wa. R Handling: When the store is executed, all ALAT-entries will be compared with the store address. Overlapping entries are removed. chk. a checks for the address of it’s corresponding advanced load in the ALAT. If the address is still there, chk. a does nothing. If it’s gone, chk. a jumps to fix-up code.

Speculative execution – fix-up The fix-up code generated by the compiler is general In case of control speculation: Not only the load is speculative, but also all instructions using the destination register. In case of data speculation: Not only the load is speculative, but also all computations before the (possibly conflicting) store. Although the compiler must include fix-up code to handle exceptions and Wa. R-conflicts, this relatively simple mechanism allows for aggressive code-motion

Comparison: ARM conditional instructions Conditional instructions to allow for branch-removal as implemented in the ARM processor (+/- 1985) Cond 000 OPC S SRC 1 DEST SH# SH SRC 2 Instruction format code ADDEQS Rd, Rn, Rm, ASL Rc Rd = Sign(Rn+(Rm << Rc)) Single cycle execution Straightforward orthogonal instruction coding: all instructions can be coded conditionally on all conditions Only 4 condition bits: Z, C, N, V in processor status register: set by CMN, CMP, TEQ, TST Flexibility: branch removal, but no code motion! (conditional instructions after CMP) 0000 EQ Z 0001 NE ~Z 0010 CS C 0011 CC ~C 0100 MI N 0101 PL ~N 0110 VS V 0111 VC ~V 1000 HI C and ~Z 1001 LS ~C or Z 1010 GE N = V 1011 LT N = ~V 1100 GT (N = V) and ~Z 1101 LE (N = ~V) or Z 1110 AL True 1111 NV False (=NOP)

In conclusion EPIC: The future of computing? As processors grow in complexity, shifting responsibilities to the compiler seems obvious Keeping up with Moore’s law: calls for conceptual innovations, not only technological

References [1] “Introducing the IA-64 architecture” J. Huck, D. Morris, J. Ross (HP), A. Knies, H. Mulder, R. Zahir (Intel) IEEE/Micro, sep-oct 2000, p. 12 -23 [2] “Itanium processor microarchitecture” H. Sharangpani, K. Arora (Intel) IEEE/Micro, sep-oct 2000, p. 24 -43 [3] “IA-64 Application developer’s architecture guide, Rev. 1. 0” Intel Documentation, may 1999 Chap. 11: “Predication, Control Flow and Instruction Stream” http: //developer. intel. com/software/idap/media/pdf/ADAG. pdf [4] “Itanium processor microarchitecture reference” Intel Documentation, aug. 2000 http: //developer. intel. com/design/ia-64/downloads/245474. htm [5] “ARM Instruction formats and timings” R. Watts, nov. 1995 http: //www. pinknoise. demon. co. uk/ARMinstrs/index. html Websites: - www. intel. com/pressroom - developer. intel. com/design/ia-64

It is now safe to ask your questions