The GBTFPGA project GBT Versatile Link FPGA Timing

The GBT-FPGA project GBT Versatile Link FPGA Timing & Trigger GBTIA DAQ GBTX PD DAQ GBLD LD Slow Control Custom ASICs On-Detector Radiation Hard Electronics Off-Detector Commercial Off-The-Shelf (COTS) • Started in 2009 as a simple proof-of-concept, Code implemented on an Altera SIIGx and a Xilinx V 5 Interoperability validated, link characterized Presented at TWEPP 2009 • Core made available, studies conducted on determinism, used to test the GBT prototype • Many requests from various teams and for various usages • Project launched in 2013, Manoel started to work on it extensively 03/02/2015 S. Baron, BE-BI & PH-ESE GBT/VL meeting 1

Pure Concept One single IP core as generic as possible to be ported on all FPGAs … 03/02/2015 S. Baron, BE-BI & PH-ESE GBT/VL meeting 2

Realistic Concept Allowing all the encoding modes offered by the GBTx … 03/02/2015 S. Baron, BE-BI & PH-ESE GBT/VL meeting 3

Reality Ensuring a low, fixed and deterministic phase and latency of the recovered clock and signals 03/02/2015 S. Baron, BE-BI & PH-ESE GBT/VL meeting 4

Augmented Reality 03/02/2015 S. Baron, BE-BI & PH-ESE GBT/VL meeting 5

2015 Status • Available Package on svn: https: //svn. cern. ch/reps/ph-ese/be/gbt_fpga – – – Core code (VHDL) Example Designs Documentation & tutorials TCL Scripts Targeting • Xilinx : Kintex 7 (FC 7, KC 705) , Virtex 7 (VC 707), Virtex 6 (GLIB) • Altera: Cyclone V (SAT, Cyclone V GT Devkit), Stratix V (AMC 40), Arria V GT (coming) – Additional Unsupported Cores (GBTx and SCA slow control) • Website: https: //espace. cern. ch/GBT-Project/GBT-FPGA/default. aspx • egroup : GBT-FPGA-users • 120 users – Some of them contributing very actively 03/02/2015 S. Baron, BE-BI & PH-ESE GBT/VL meeting 6