The Devices MOS Transistor Dynamics Adapted from Rabaeys

Overview - Transistor Dynamics Transistor capacitances l Sub-Micron MOS Transistor l » Threshold Variations » Velocity Saturation » Sub-Threshold Conduction and Leakage Latchup l Process Variations l Future Perspectives l EE 415 VLSI Design

Dynamic Behavior of MOS Transistor • MOSFET is a majority carrier device (unlike pn junction diode) • Delays depend on the time to (dis)charge the capacitances between MOS terminals • Capacitances originate from three sources: • basic MOS structure (layout) • charge present in the channel • depletion regions of the reverse-biased pnjunctions of drain and source • Capacitances are non-linear and vary with the applied voltage EE 415 VLSI Design

MOS Structure Capacitances Gate Capacitance • Gate isolated from channel by gate oxide Gate Oxide Gate Source • tox is very small <10 nm • Results in gate capacitance Cg Polysilicon n+ Drain Field-Oxide n+ (Si. O 2) p-substrate Bulk Contact CROSS-SECTION of NMOS Transistor EE 415 VLSI Design p+ stopper

The Gate Capacitance EE 415 VLSI Design

The Gate Capacitance depends on • channel charge (non-linear) • topology Capacitance due to topology • Source and drain extend below the gate oxide by xd (lateral diffusion) • Effective length of the channel Leff is shorter than the drawn length by factor of 2 xd • Cause of parasitic overlap capacitance, Cgs. O, between gate and source (drain) EE 415 VLSI Design

The Gate Capacitance Overlap Capacitance EE 415 VLSI Design Channel Capacitance

The Channel Capacitance has three components • capacitance between gate and source, Cgs • capacitance between gate and drain, Cgd • capacitance between gate and bulk region, Cgb Channel Capacitance values • non-linear, depends on operating region • averaged to simplify analysis EE 415 VLSI Design

The Channel Capacitance Different distributions of gate capacitance for varying operating conditions Most important regions in digital design: saturation and cut-off EE 415 VLSI Design

Diffusion Capacitance Bottom Plate Capacitance Junction Depth EE 415 VLSI Design

Capacitive Device Model G CGS = Cgs+ Cgs. O CGS CGD = Cgd+ Cgd. O CGB = Cgb CSB = CSdiff CGD D S CGB CSB CDB = CDdiff B EE 415 VLSI Design CDB

Transistor Capacitance Values for 0. 25 Example: For an NMOS with L = 0. 24 m, CGSO = CGDO = Cox xd W = Co W = 0. 11 f. F W = 0. 36 m, LD = LS = 0. 625 m CGC = Cox WL = 0. 52 f. F Capacitance of both source and drain so Cgate_cap = Cox. WL + 2 Co. W = 0. 74 f. F Cbp = Cj LS W = 0. 45 f. F Csw = Cjsw (2 LS + W) = 0. 45 f. F so Cdiffusion_cap = 0. 90 f. F Overlap capacitance Cox (f. F/ m 2) Co (f. F/ m) Cj (f. F/ m 2) mj b (V) Cjsw (f. F/ m) mjsw bsw (V) NMOS 6 0. 31 2 0. 5 0. 9 0. 28 0. 44 0. 9 PMOS 6 0. 27 1. 9 0. 48 0. 9 0. 22 0. 32 0. 9 EE 415 VLSI Design

Review: Sources of Capacitance Vout Vin CG 4 M 2 CGD 12 Vin pdrain ndrain M 1 CDB 2 CDB 1 M 4 Vout 2 Cw CG 3 intrinsic MOS transistor capacitances extrinsic MOS transistor (fanout) capacitances wiring (interconnect) capacitance EE 415 VLSI Design Vout 2 CL M 3

Gate-Drain Capacitance: The Miller Effect l l M 1 and M 2 are either in cut-off or in saturation. The floating gate-drain capacitor is replaced by a capacitance-to-ground (gate-bulk capacitor). V CGD 1 Vin V M 1 l Vout 2 CGB 1 V Vin V M 1 A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground whose value is two times the original value EE 415 VLSI Design

Drain-Bulk Capacitance: Keq’s (for 2. 5 m) l We can simplify the diffusion capacitance calculations even further by using a Keq to relate the linearized capacitor to the value of the junction capacitance under zero-bias Ceq = Keq Cj 0 NMOS PMOS EE 415 VLSI Design high-to-low Keqbp Keqsw 0. 57 0. 61 0. 79 0. 86 low-to-high Keqbp Keqsw 0. 79 0. 81 0. 59 0. 7

Extrinsic (Fan-Out) Capacitance l The extrinsic, or fan-out, capacitance is the total gate capacitance of the loading gates M 3 and M 4. Cfan-out = Cgate (NMOS) + Cgate (PMOS) = (CGSOn+ CGDOn+ Wn. Ln. Cox) + (CGSOp+ CGDOp+ Wp. Lp. Cox) l Simplification of the actual situation » Assumes all the components of Cgate are between Vout and GND (or VDD) » Assumes the channel capacitances of the loading gates are constant EE 415 VLSI Design

Layout of Two Chained Inverters VDD PMOS 1. 125/0. 25 1. 2 m =2 l Out In Metal 1 Polysilicon 0. 125 0. 5 NMOS 0. 375/0. 25 GND W/L AD ( m 2) PD ( m) AS ( m 2) PS ( m) NMOS 0. 375/0. 25 0. 3 1. 875 PMOS 1. 125/0. 25 0. 7 2. 375 EE 415 VLSI Design

Components of CL (0. 25 m) Expression C Term Value (f. F) H L L H CGD 1 2 Con Wn 0. 23 CGD 2 2 Cop Wp 0. 61 CDB 1 Keqbpn. ADn. Cj + Keqswn. PDn. Cjsw 0. 66 0. 90 CDB 2 Keqbpp. ADp. Cj + Keqswp. PDp. Cjsw 1. 5 1. 15 CG 3 (2 Con)Wn + Cox. Wn. Ln 0. 76 CG 4 (2 Cop)Wp + Cox. Wp. Lp 2. 28 Cw from extraction 0. 12 CL 6. 1 6. 0 EE 415 VLSI Design

The Sub-Micron MOS Transistor • Actual transistor deviates substantially from model • Channel length becomes comparable to other device parameters. Ex: depth of drain and source junctions • Referred to as a short-channel device • Influenced heavily by secondary effects • Latchup problems EE 415 VLSI Design

The Sub-Micron MOS Transistor Secondary Effects: • Threshold Variations • Parasitic Resistances • Velocity Saturation • Mobility Degradation • Sub-threshold Conduction EE 415 VLSI Design

Threshold Variations • Part of the region below gate is depleted by source and drain fields, which reduce threshold voltage for short channel. • Similar effect is caused by increase in VDS, so threshold is smaller with larger VDS VT VT Long-channel threshold L Threshold as a function of the length (for low VDS) EE 415 VLSI Design Low VDS threshold VDS Drain-induced barrier lowering lowers VT for short channel device

Variations in I-V Characteristics • The velocity of the carriers is proportional to the electric field up to a point. • When electric field reaches a critical value, Esat, the velocity saturates. • When the channel length decreases, only a small VDS is needed for saturation • Causes a linear dependence of the saturation current wrt the gate voltage (in contrast to squared dependence of long-channel device) • Current drive cannot be increased by decreasing L EE 415 VLSI Design

u n (m/s) Velocity Saturation usat = 105 Constant velocity Constant mobility (slope = µ) c = 1. 5 EE 415 VLSI Design (V/µm)

Velocity Saturation l l We assumed carrier velocity is proportional to E-field » v = Elat = Vds/L At high fields, this ceases to be true » Carriers scatter off atoms » Velocity reaches vsat – Electrons: 6 -10 x 106 cm/s – Holes: 4 -8 x 106 cm/s » Better model EE 415 VLSI Design

Voltage-Current Relation: Velocity Saturation For short channel devices l Linear: When VDS VGS – VT ID = (VDS) k’n W/L [(VGS – VT)VDS – VDS 2/2] where (V) = 1/(1 + (V/( c. L))) is a measure of the degree of velocity saturation l Saturation: When VDS = VDSAT VGS – VT IDSat = (VDSAT) k’n W/L [(VGS – VT)VDSAT – VDSAT 2/2] EE 415 VLSI Design

Velocity Saturation Effects VGS = VDD Long channel devices Short channel devices VDSAT VGS-VT For short channel devices and large enough VGS – VT VDSAT < VGS – VT so the device enters saturation before VDS reaches VGS – VT and operates more often in saturation l IDSAT has a linear dependence wrt VGS so a reduced amount of current is delivered for a given control voltage l EE 415 VLSI Design

Velocity Saturation EE 415 VLSI Design

Short Channel I-V Plot (NMOS) NMOS transistor, 0. 25 um, Ld = 0. 25 um, W/L = 1. 5, VDD = 2. 5 V, VT = 0. 4 V X 10 -4 VGS = 2. 5 V ID (A) VGS = 2. 0 V Linear Saturation VGS = 1. 5 V VGS = 1. 0 V EE 415 VLSI Design VDS (V) Linear dependence Early Velocity Saturation

Leakage Sources l l Subthreshold conduction » Transistors can’t abruptly turn ON or OFF Junction leakage » Reverse-biased PN junction diode current Gate leakage » Tunneling through ultrathin gate dielectric Subthreshold leakage is the biggest source of DC power dissipation in modern transistors EE 415 VLSI Design D D S S

Sub-Threshold Conduction -2 The Slope Factor 10 Linear -4 10 -6 10 Quadratic ID (A) S is VGS for ID 2/ID 1 =10 -8 Slope S 10 -10 Exponential -12 VT 10 10 0 0. 5 1 1. 5 VGS (V) EE 415 VLSI Design 2 2. 5 Typical values for S: 60. . 100 m. V/decade

Gate Leakage l l Carriers tunnel thorough very thin gate oxides Exponentially sensitive to tox and VDD D IG S l l » A and B are tech constants » Greater for electrons – So n. MOS gates leak more From [Song 01] Negligible for older processes (tox > 20 Å) Critically important at 65 nm and below (tox ≈ 10 Å=1 nm) EE 415 VLSI Design

Sub-Threshold ID vs VGS D ID VG + - VS VDS from 0 to 0. 5 V EE 415 VLSI Design VGS

Sub-Threshold ID vs VDS VD I D VG VS VGS from 0 to 0. 3 V EE 415 VLSI Design

ID versus VGS -4 6 x 10 -4 x 10 2. 5 5 2 4 linear quadratic ID (A) 1. 5 3 1 2 0. 5 1 quadratic 0 0 0. 5 1 1. 5 VGS(V) Long Channel EE 415 VLSI Design 2 2. 5 0 0 0. 5 1 1. 5 VGS(V) Short Channel 2 2. 5

ID versus VDS -4 6 -4 x 10 VGS= 2. 5 V x 10 2. 5 VGS= 2. 5 V 5 2 Resistive Saturation ID (A) VGS= 2. 0 V 3 VDS = VGS - VT 2 1 VGS= 1. 5 V 0. 5 VGS= 1. 0 V VGS= 1. 5 V 1 0 0 VGS= 2. 0 V 1. 5 ID (A) 4 VGS= 1. 0 V 0. 5 1 VDS(V) 1. 5 Long Channel EE 415 VLSI Design 2 2. 5 0 0 0. 5 1 VDS(V) 1. 5 Short Channel 2 2. 5

A unified model for manual analysis G S D B VT 0(V) (V 0. 5) VDSAT(V) k’(A/V 2) (V-1) NMOS 0. 43 0. 4 0. 63 115 x 10 -6 0. 06 PMOS -0. 4 -1 -30 x 10 -6 -0. 1 EE 415 VLSI Design

A PMOS Transistor PMOS transistor, 0. 25 um, Ld = 0. 25 um, W/L = 1. 5, VDD = 2. 5 V, VT = -0. 4 V -4 0 x 10 -0. 2 ID (A) -0. 4 VGS = -1. 0 V VGS = -1. 5 V VGS = -2. 0 V Assume all variables negative! -0. 6 VGS = -2. 5 V -0. 8 -1 -2. 5 EE 415 VLSI Design -2 -1. 5 -1 VDS (V) -0. 5 0

Parasitic Resistances Polysilicon gate G LD increase W Drain contact D S RS W VGS, eff RD Drain RSQ is the resistance per square RC is the contact resistance EE 415 VLSI Design Silicide the bulk region

The Transistor as a Switch VGS VT S Ron D EE 415 VLSI Design

The Transistor as a Switch VGS VT x 105 Ron D Req (Ohm) S Resistance inversely proportional to W/L (doubling W halves Ron) l For VDD>>VT+VDSAT/2, Ron independent of VDD l Once VDD approaches VT, Ron increases dramatically l VDD (V) VDD(V) 1 1. 5 2 2. 5 NMOS(k ) 35 19 15 13 PMOS (k ) 115 55 38 31 EE 415 VLSI Design (for VGS = VDD, VDS = VDD/2) Ron (for W/L = 1) For larger devices divide Req by W/L

Summary of MOSFET Operating Regions l Strong Inversion VGS > VT » Linear (Resistive) VDS < VDSAT » Saturated (Constant Current) VDSAT l Weak Inversion (Sub-Threshold) VGS VT » Exponential in VGS with linear VDS dependence EE 415 VLSI Design

Latchup EE 415 VLSI Design

Fitting level-1 model to short channel characteristics EE 415 VLSI Design

SPICE MODELS Berkeley Short-Channel IGFET Model EE 415 VLSI Design

MAIN MOS SPICE PARAMETERS EE 415 VLSI Design

SPICE Parameters for Parasitics EE 415 VLSI Design

Simple Model versus SPICE 2. 5 x 10 -4 VDS=VDSAT 2 Velocity Saturated ID (A) 1. 5 Linear 1 VDSAT=VGT 0. 5 VDS=VGT 0 0 0. 5 Saturated 1 1. 5 VDS (V) EE 415 VLSI Design 2 2. 5

Technology Evolution l Semiconductor Industry Association forecast » Intl. Technology Roadmap for Semiconductors EE 415 VLSI Design

Process Variations Devices parameters vary between runs and even on the same die! Variations in the process parameters, such as impurity concentration densities, oxide thicknesses, and diffusion depths. These are caused by nonuniform conditions during the deposition and/or the diffusion of the impurities. Introduces variations in the sheet resistances and transistor parameters such as the threshold voltage. Variations in the dimensions of the devices, resulting from the limited resolution of the photolithographic process. This causes (W/L) variations in MOS transistors and mismatches in the emitter areas of bipolar devices. EE 415 VLSI Design

Impact of Device Variations 2. 10 Delay (nsec) 1. 90 1. 70 1. 50 1. 10 1. 20 1. 30 1. 40 1. 50 1. 60 Leff (in m) 1. 50 – 0. 90 – 0. 80 – 0. 70 – 0. 60 – 0. 50 VTp (V) Delay of Adder circuit as a function of variations in L and VT EE 415 VLSI Design

So What? l So what if transistors are not ideal? » They still behave like switches. l But these effects matter for… » Supply voltage choice » Logical effort » Quiescent power consumption » Pass transistors » Temperature of operation EE 415 VLSI Design

Parameter Variation l Transistors have uncertainty in parameters » Process: Leff, Vt, tox of n. MOS and p. MOS » Vary around typical (T) values l l l Fast (F) » Leff: ____ » Vt: ____ » tox: ____ Slow (S): opposite Not all parameters are independent for n. MOS and p. MOS EE 415 VLSI Design

Parameter Variation l Transistors have uncertainty in parameters » Process: Leff, Vt, tox of n. MOS and p. MOS » Vary around typical (T) values l l l Fast (F) » Leff: short » Vt: low » tox: thin Slow (S): opposite Not all parameters are independent for n. MOS and p. MOS EE 415 VLSI Design

Environmental Variation l l VDD and T also vary in time and space Fast: » VDD: ____ » T: ____ Corner Voltage Temperature 1. 8 70 C F T S EE 415 VLSI Design

Environmental Variation l l VDD and T also vary in time and space Fast: » VDD: high » T: low Corner Voltage Temperature F 1. 98 0 C T 1. 8 70 C S 1. 62 125 C EE 415 VLSI Design

Process Corners l l Process corners describe worst case variations » If a design works in all corners, it will probably work for any variation. Describe corner with four letters (T, F, S) » n. MOS speed » p. MOS speed » Voltage » Temperature EE 415 VLSI Design

Important Corners l Some critical simulation corners include Purpose Cycle time Power Subthrehold leakage EE 415 VLSI Design n. MOS p. MOS VDD Temp

Important Corners l Some critical simulation corners include Purpose n. MOS p. MOS VDD Temp Cycle time S S Power F F Subthrehold leakage F F F S EE 415 VLSI Design

Future Perspectives 25 nm FINFET MOS transistor EE 415 VLSI Design

Three-Dimensional Integrated Circuits l l Multiple Layers of Active Devices Driven by » Limited floorplanning choices » Desire to integrate disparate technologies (Ga. As, SOI, Si. Ge, Bi. CMOS) » Desire to integrate disparate signals (analog, digital, RF) » Interconnect bottleneck 3 D IC 2 D IC As small as 20µm EE 415 VLSI Design >500µm 60