THE DESIGN OF THE MEMORY BUILTIN SELFTEST DIAGNOSIS

THE DESIGN OF THE MEMORY BUILT-IN SELF-TEST, DIAGNOSIS AND REPAIR (MBISTDR) FOR SRAMs By WAN ZUHA WAN HASAN (UPM) DEPARTMENT OF ELECTRICAL, ELECTRONIC AND SYSTEM, FACULTY OF ENGINEERING UKM Supervised by PROF DR MASURI OTHMAN (UKM) Co-supervisor DR BAMBANG SUNARYO SUPARJO (MENTOR GRAPHIC USA)

Outline • Introduction • Memory Architecture • Memory Fault Models • Test Algorithms • Memory Testing, Diagnosis and Repair • Conclusion

Introduction Why BIST, BISD and BISR The advances of semiconductor memory technologies have become more complex and also the numbers of memory cell per chip (transistors) rapidly increase. The ITRS 2003 has shown an ever Increasing percentage of chip area devoted to embedded memory, with today’s So. Cs already consisting of over 50% memory.

Introduction

Introduction Memory Sizes Versus Yield

Introduction ITRS 2004 - SOC Test Requirements

Introduction The Requirement of Future MBISTDR • Fault Modeling – New Fault Models (defect in deep-submicron) • Test algorithm design – Optimal test/diagnosis (high defect coverage) • BIST – allow at speed testing • BISR – low cost repair scheme ( improve the yield and reliability)

Memory architecture Functional RAM Model Source: Testing and semiconductor memories, A. J. van de Goor

Memory architecture Reduced Functional RAM Model Source: Testing and semiconductor memories, A. J. van de Goor

Memory Fault Models Source: Testing and semiconductor memories, A. J. van de Goor

Memory Fault Models

Memory Fault Models Coupling Fault(CF)

Memory Fault Models Two Cell Faults - cont

Memory Fault Models

Memory Fault Models Coupling Fault State Coupling Fault Source: Testing and semiconductor memories, A. J. van de Goor

Memory Fault Models

Test Algorithms Functional RAM Testing • Traditional Test - Zero-One - SAF - Checkerboard - SAF - GALPAT and Walking 1/0 – AF, SAF, TF and CF - testing time unacceptable - Sliding Diagonal – SAF, TF - Butterfly – SAF, AF Source: Testing and semiconductor memories, A. J. van de Goor

Test Algorithms March Test Algorithms

Test Algorithms March Test Notation Source: Testing and semiconductor memories, A. J. van de Goor

Test Algorithms Source: Testing and semiconductor memories, A. J. van de Goor

Test Algorithms Comparison of March Tests March Test Algorithm Number Operation Fault Coverage Test-US MATS 4 n or * 2 N SAF, some AF MATS+ 2 5 n or 5 * 2 N SAF, AF Test-UT MATS++ 7 or 7 * 2 N SAF, TF, AF Test-UC March C 11 n SAF, TF, AF, CF Test-LC March A 15 n SAF, CF Test-LCT March B 17 n SAF, CF, TF Source: Testing and semiconductor memories, A. J. van de Goor

Test Algorithms Fault detection using March CM 0 M 1 M 2 M 3 {⇕(w 0); (r 0, w 1); (r 1, w 0); (r 0, w 1); M 4 M 5 (r 1, w 0); ⇕(r 0} - 10 N Test algorithm Disable RAM (wait) { (r 0, w 1, ); Disable RAM(wait) (r 1): } - Data retention fault(DRF)

Test Algorithms Fault detection using Extended March C- (covered SOF) M 0 M 1 M 2 M 3 {⇕(w 0); (r 0, w 1, r 1); (r 1, w 0); (r 0, w 1); M 4 M 5 (r 1, w 0); ⇕(r 0)} - 11 N Test algorithm Disable RAM (wait) { (r 0, w 1, ); Disable RAM(wait) (r 1): } - Data retention fault(DRF)

Test Algorithms Fault detection using extended March CMarch Elements Fault M 0 M 1 M 2 M 3 M 4 M 5 ⇕(w 0) (r 0, w 1, r 1) (r 1, w 0) (r 0, w 1) (r 1, w 0) ⇕(r 0) r 0 – s-a-1 r 1 – s-a-0 SAF TF CF AF SOF DRF I N I T I A L Z A T I O N M 1(r 0, w 1) followed by M 2(r 1) for < /0> M 2(r 1, w 0) followed by M 3(r 0) for < /1> M 1(r 0, w 1) for Cfid < /1> *j<i M 1 followed by M 2 for Cfin < /↕> M 2(r 1, w 0) for Cfid < /0> *j<i M 2(r 1, w 0) for Cfin < /↕> *j>i M 3(r 0, w 1) followed by M 4(r 1, w 0) Cfid < /0> M 1 & M 3(r 0, w 1) Followed by M 4(r 1, w 0) for Cfin < /↕> *all CFids is j<i M 4(r 1, w 0) followed by M 5(r 0) for Cfid for < /1> M 2 & M 4(r 1, w 0) followed by M 5(r 0) for Cfin < / ↕ > ( for j>i is similar) (M 1(r 0, w 1, r 1) M 2(r 1, w 0)) – j>i, (M 3(r 0, w 1) M 4 (r 1, w 0)) – i>j (Satisfied with known technology) r 1 Disable RAM (wait) { (r 0, w 1, ); Disable RAM(wait) (r 1): }

Test Algorithms Functional Fault Models for Diagnosis ICCAD 2000 Chi-Feng Wu

Test Algorithms Fault detection and diagnosis using March CL { (w 0); (r 0, w 1, ); (r 1, w 0, ); ⇕(r 1); R 0 R 1 (r 0, w 1); ⇕(r 1); (r 1, w 0); ⇕(r 0)} R 3 R 4 R 5 R 2 R 6 -12 N Test algorithm Disable RAM (wait){ (r 0, w 1, ); Disable RAM(wait) (r 1): } - Data retention Fault(DRF).

Test Algorithms Fault detection and diagnosis by Extended March CL { (w 0); (r 0, w 1, r 1); (r 1, w 0); ⇕(r 1); R 0 R 1 R 2 (r 0, w 1); ⇕(r 1); (r 1, w 0); ⇕(r 0)} R 4 R 5 R 6 R 3 R 7 -13 N Test algorithm Disable RAM (wait){ (r 0, w 1, ); Disable RAM(wait) (r 1): }- Data retention Fault(DRF).

Test Algorithms Fault syndrome for March CL

Test Algorithms Fault syndrome for Extended March CL

Test Algorithms Existing March Test Algorithms 1. { (w 0); (r 0, w 1, ); (r 1, w 0); (r 0, w 1); (r 1, w 0) }Disable RAM (wait){ (r 0, w 1, ); Disable RAM(wait) (r 1): } 9 N test algorithm with data retention test – Rob Dekker 1988, has covered 100% coverage of the faults under the listed fault models. 2. { (w 0); (r 0, w 1, r 1, w 0); delay (r 0, r 0); (w 1); (r 1, w 0, r 0, w 1); delay (r 1, r 1)} 14 N test algorithm - Said Hamdioui 2000, has covered 100% coverage of the faults under the listed fault models and spot defects.

Test Algorithms Existing March Test Algorithms 3. { (w 0); (r 0); delay (r 0); (w 1); (r 1); delay (r 1)} or { (w 0); (r 0); delay (r 0); (w 1); (r 1); delay (r 1)} 6 N test algorithm – Baosheng Wang 2003, has reduced less than half of the required time for the 9 N test algorithm 4. { ⇕(w 0); (r 0, w 1, ); ⇕(r 1); (r 1, w 0); ⇕(r 0); (r 0, w 1); ⇕(r 1); (r 1, w 0); ⇕(r 0); 13 N test algorithm – V. N. Yarmolik 1996, has introduced diagnosis capability and achieved 63. 6% diagnostic resolution (SAF & CF).

Test Algorithms Existing March Test Algorithms 5. { ⇕(w 0); (r 0, w 1, r 1, w 0); (r 0, w 1); (r 1, w 0, r 0, w 1); ⇕(r 1); (r 1, w 0); ⇕(r 0); (r 0, w 1); ⇕(r 1); 18 N test algorithm – V. N. Yarmolik 1996, has been introduced for the diagnosis capability and achieved 90. 9%diagnostic resolution (SAF & CF). 6. { (w 0); (r 0, w 1, w 0, w 1); (r 1, w 0, r 0, w 1); (r 1, w 0, w 1, w 0); (r 0, w 1, r 1, w 0); Hold (r 0, w 1); Hold (r 1); 20 N test algorithm – I. Kim 1998, has been diagnosis capability and achieved 59% diagnostic resolution (SAF

Test Algorithms Existing March Test Algorithms 7. { (w 0); (r 0, w 1, r 1, w 0 ); ⇕(r 0); ⇕(w 1); (r 1, w 0, r 0, w 1); ⇕(r 1); } 12 N test algorithm – T. J. Bergfeld 2000, has proposed diagnosis capability but it could only achieve 22. 7% diagnostic resolution (SAF & CF). 8. { ⇕(w 0); (r 0, w 1, r 1); ⇕(r 1); (r 1, w 0, r 0); ⇕(r 0); } 17 N test algorithm – Jin-Fu Li 1996, has introduced diagnosis capability and achieved 100% diagnostic resolution(SAF & CF).

Test Algorithms Existing March Test Algorithms 9. { (w 0); (r 0, w 1, ); ⇕(r 1); (r 1, w 0); (r 0, w 1); ⇕(r 1); (r 1, w 0); ⇕(r 0); } 12 N test algorithm plus 3 N or 4 N ( for aggressor locating) – V. A. Vardanian 2002, has introduced diagnosis capability and achieved 100% diagnostic resolution.

Test Algorithms STATE-OF-ART FOR TEST ALGORITHMS • Optimality in term of time complexity • Regularity and symmetry such that the self-test circuit can minimize the silicon area • High defect coverage and diagnosis capability in order to increase the repair capabilities and the overall yield

Memory Testing, Diagnosis and Repair MBIST ARCHITECTURE BIST CONTROLLER FSM COMPARATOR SRAM MBIST SYSTEM

Memory Testing, Diagnosis and Repair MBISTD ARCHITECTURE BIST CONTROLLER FSM COMPARATOR INDICATOR SRAM MBISTD SYSTEM

Memory Testing, Diagnosis and Repair BISTD STATE-OF-ART FOR BISTD • Minimizing BIST overhead in both silicon area and routing • Supporting diagnosis capabilities • Supporting different kinds of memories (single-port, multi-port)

Memory Testing, Diagnosis and Repair MBISTDR ARCHITECTURE BIST CONTROLLER FSM COMPARATOR INDICATOR SRAM EXTRA COLUMN /ROW/WORD MBISTDR SYSTEM

Conclusion MBISTDR is essential for memory reliability in the near future. The addition of BISD and BISR will enhance the yields of overall memory chips. New test algorithm and fault syndromes base on March CL has been proposed to detect and diagnose SOF and AF.

THANK YOU Q&A

Memory Testing, Diagnosis and Repair Example of MBISR Data Address Control MBIST Mux Fuse Box Redundancy Logic RAM Mux Data The Memory BIST and Self-Repair (MBISR) Concept [Volker 2001].

Memory Testing, Diagnosis and Repair • The Figure above shows the MBIST and Self-Repair using redundancy logic and Fuse Box concept. • The MBISR concept contains an interface between MBIST logic, redundancy wrapper logic to replace defect address and Fuse boxes to store the failling addresses

On Going Research The design and simulation of MBISTDR. New Test Algorithms with Diagnosis capability will be designed according to the required coverage and testing time.

MBISTDR Methodology d_in addr 5 bistr_data_write 12 12 MUX_1 bistr_en clk mode_sel 5 Bistr_error_addr 5 Bistr_add r Wr_en MBISTDR CONTROLLER Rd_en 12 32 X 12 SRAM Sram_error 12 Mode_sel MUX_2 bistr_data_read 5 d_out 12 Design of MBISTDR Controller for Stuck-at Faults

MBISTDR Methodology The schematic of MBISTDR Controller for Stuck-at Faults

MBISTDR Methodology Figure above shows that MBISTDR contains MBISTDR controller and 32 x 12 SRAM Test Pattern In – Bistr_data_write (w 0/w 1) Mode_sel – test or normal mode Enable the Wr_en or Rd_en Test Pattern Out – Bistr_data_read(r 0/r 1)

MBISTDR Methodology Test and Repair Algorithm of MBISTDR controller for Stuck-at Faults

MBISTDR Methodology Figure above Shows that, how MBISTR controller implements the test and repair algorithm to the 32 x 12 SRAM memory. Procedure: address 1 – w 0 then compare with r 0 address 2 – w 1 then compare with r 1 Run until either marked addresses or memory addresses reach the maximum

MBISTDR Results And Discussion Fault Free Results for MBISTDR During Normal mode Operation

MBISTDR Result And Discussion Fault Detection Results for MBISTDR during Test mode Operation

MBISTDR Result And Discussion Results for MBISTDR During Normal Mode and Test Mode Operation

Final Target for MBISTDR Criteria: TA 1) High defect coverage and diagnosis capability in order to increase the repair capabilities and the overall yield – below 17 N 2) BISTDR 3) 1)Supporting diagnosis capabilities – 100% diagnosis resolution (include SOF and AF) 4) 2) Using Extra Memory for the BISR

MBISTDR Conclusion A new memory Built-in Self-test and Repair concept has been designed and this concept is proposed without using any extra rows and columns. These test and repair are only focused on the reconfiguration of the memory addresses, which means no extra spaces needed as the previous researches.