The AMD Athlon Processor Future Directions Fred Weber

The AMD Athlon™ Processor: Future Directions Fred Weber Vice President, Engineering Computation Products Group

Workstation & Server Capabilities 72 -Pin Data Bus w/ ECC u Scales to 43 -bit Physical Address 72 b u DATA 13 -Pin Snoop Bus System Logic DRAM u Snoops/Sys. CMD 13 -Pin Address Bus PCI u 72 b Up to 24 Outstanding Transactions per Processor AMD Athlon™ Processor DATA u L 2 CACHE AMD Athlon™ Processor AGP Backside L 2 Cache interface supports up to 8 MB Snoops/Sys. CMD u L 2 CACHE Requests 200 MHz FSB (1. 6 GB/sec) that can scale to 400 MHz (3. 2 GB/sec) per processor Requests u Forward Clocks

Product Features In 2000 u Processor Scalability · 1 MB and 2 MB Full Speed, 16 -way associative L 2 Cache · 266 MHz Front Side Bus u System Scalability: 2 -way; 4 to 8 way multiprocessing · AMD: 2 processor design · 266 MHz Front Side Bus with DDR DRAM (PC-2100™ ) · 4 X AGP-Pro, PCI 66/64 · Multi-way: Infrastructure development underway (API and Hot. Rail) u Reliability · ECC Protected L 2 Cache, DRAM and Front Side Bus · Execution Signature Generation

LDT The System Bus of the Future

AMD’s System Bus Initiative: Lightning Data Transport (LDT) u Goals · Simplify design and flexibility with a single data link for “inchassis” connection to I/O, multi-processing and coprocessors · Improve system performance with increased I/O performance and scalable bandwidth · Enable flexibility of system I/O technologies through a modular bridge architecture · Complement externally visible bus standards

AMD’s LDT: I/O u I/O can be daisy chained · Multiple bridges on a single I/O link · Multiple “pass through” devices can be interconnected · Bridges are independent (reusable for many designs) u The System I/O SANIC (HCA) is independent of the memory controller AMD Athlon™ EV 6 Bus DRAM North Bridge AGP LDT SIO SANIC PCI 66/64 PCI-X Southbridge PCI 33/32

AMD’s LDT: Multiprocessing u Multiple LDT System Links (I/O) Coherent link provides scalable multiprocessing u Memory capacity scales u Memory bandwidth scales u I/O capacity scales u I/O bandwidth scales AMD Athlon™ DRAM AMD Athlon™ EV 6 Bus North Bridge DRAM EV 6 Bus LDT DRAM AMD Athlon™ AMD ™ Athlon™ Multiple LDT System Links (I/O)

LDT Features Ctrl Clk Up to 1. 6 Gbits/sec per pin 8, 16 or 32 - bits in each direction Ctrl Clk Isochronous Transfer Receive Priority to ensure They Arrive On Time u Unidirectional point-to-point links in each direction · Differential signaling with source synchronous clock forwarding u Variable widths negotiated at initialization · Upstream and downstream links can be of different size u 16/16 -bit link provides 6. 4 GB/sec each way u Multiple logical channels in each link · Guaranteed isochronous bandwidth u In-band system management and legacy signal transport u PCI like configuration mechanism