The Abstract simulator SimulatorSimulation Concepts n Simulator responsible
The Abstract simulator
Simulator/Simulation Concepts n Simulator: responsible for executing a model’s dynamics (resented as instructions) in a given formalism. n Abstract simulator: a characterization of what needs to be done in executing a model’s instructions – atomic simulator – coupled simulator n Simulation engines: enforce particular realizations of abstract simulator n Simulations can be executed as: – – Sequential Parallel Distributed (sequential/parallel) Real-Time
Standard DES mechanisms < Event list > Time Event routine t 1 E 1 : : Transition: event generation until event list empty – Simulation performance : event list management • event list: insert, delete, location • search time: not constant (solution : priority queue implementation heap)
Abstract simulation : Hierarchical simulation (scheduling) algorithm (i) Concept : separation of control (scheduling) algorithm from data(model) User’s spec ABC AB A C: ABC request C B System’s simulation algorithm Ack C: AB S: A S: C S: B Passive agent (data) Active agent (control) server client S : C : simulator for model C (simulation algorithm) C: AB : Coordinator for model AB (simulation algorithm) (ii) Hierarchical scheduling No global event list
Processors: two types of simulation entities (iii) Two classes of simulations simulator class Associated with atomic DEVS ( int, ext, ta, ) invoke coordinator class Associated with coupled DEVS Event routing Hierarchical scheduling < GEN-BUF-PROC model > <BUF-PROC model> GEN out in done BUFFER out in PROC out
Simulation entities example
Message passing z External Events z Internal Events
Types of messages involved and their interaction (x, t) (*, t) S : GEN C: GENBUFPROC (done, t. N) (x, t) (*, t) C: BUFPROC (done, t. N) S : BUF (x, t) (*, t) (done, t. N) S : PROC (x, t) : external input event arrival at time t (*, t) : internally-generated event at time t that notifies the scheduled time is completely elapsed (done, t. N) : synchronization event generated at time t. N that notifies the next scheduled time is t. N
Simulator and Coordinator activities (x, t) (*, t) Simulator for AM Wait (done, t. N) (x, t) When receive (x, t), invoke ext and ta setting When receive (*, t), invoke int , and ta setting M: ext (*, t) (done, t. N) M: int ta SELECT needed Wait (x, t) (*, t) (done, t. N) Coordinator for CM (x, t) (done, t. N) Route (x, t) wait till done (done, t. N) schedule Minimum t. N (*, t) Route(*, t) imminent(i*) component Wait i* done and (x, t) from i* done
Coordinator activities Wait (x, t) (*, t) (x, t) t. L t. N Coordinator (done, t. N) Route (x, t) wait till done (done, t. N) schedule (*, t) Route(*, t) imminent(i*) component Wait i* done and (x, t) from i* done When receive (*, t) When receive (x, t) if t = t. N then if t. L t t. N then find component(s) with t. N send (x, t) to connected component(s) select one i* wait all component(s) done send (*, t) to i* t. L : = t wait response: (yi, port) t. N : = min{t. Ni | i: component} translate yi* to x send (done, t. N ) to upper level coordinator send x to its influencees else error wait i* and its influencees done t. L : = t t. N : = min{t. Ni | i: i* + its influencees } send (done, t. N ) to upper level coordinator else error
Coordinator: example GEN+BUF+PROC out GEN in out done in out BUF PROC Root SELECT GEN C : G+B+P 1 2 3 4 5 6 7 8 ta(BUF) ta(PROC) : 2 1 3 2 1 : 1 2 1 3 2 S: G C : B+P G B B S: P G P P P
Coordinator: example (contd. ) C : G+B+P ROOT t 1 2 3 0 3 (s) int(s) (6) ext(s) ta = 1 ta = 2 2 1 t=1 S : GEN (done, t. N=1) (*, 1) S : BUF S : PROC C : B+P (5) Route: S: BUF t. N=3 schedule t. N=2 (done, 2) 1 2 3 (*, 2) 3 (s) int(s) ta = 2 2 1 ext(s) ta = 1 t. N=4 t. N=3 schedule t. N=3 (4) Route: C: B+P t. N=3 (done, 3) 1 2 3 (*, 3) 3 (S) int(s) ta = 1 2 1 t. N=4 (done, 4) 1 2 3 3 (s) int(s) ta = 2 2 1 2 3 schedule (done, 4) t. N=6 t. N=4 ext(s) ta = 2 t. N=4 1 t=3 ext(s) ta =1 schedule (*, 4) t. N=4 t=2 t. N=4 t=4
Note on abstract simulator 1. Modeler has no responsibility in time control No worry about execution sequence (No explicit initial state) 2. Separation of characteristic functions in modeling simplicity, reusability 3. Close under coupling operation Example of 2 : Buffer BUF FIFO LIFO (First-in, First-out) (Last-in, First-out) insert ext : X Q S int : S S : S Y ta : S R+0, delete FIFO reusable insert LIFO
Generator CD++ - Simulation Mensaje Mensaje Mensaje Mensaje Mensaje I I D D * * Y D Y D * / / / / / 00: 00: 00: 000 00: 00: 00: 000 00: 00: 00: 000 00: 00: 03: 324 00: 00: 03: 324 00: 05: 632 / / / / / Root(00) para top(01) para gen(02) / 00: 00: 000 para top(01) / 00: 00: 000 para Root(00) para top(01) para gen(02) / out / 0. 000 para top(01) gen(02) / 00: 03: 324 para top(01) / out / 0. 000 para Root(00) top(01) / 00: 03: 324 para Root(00) para top(01) para gen(02) / out / 1. 000 para top(01) gen(02) / 00: 02: 308 para top(01) / out / 1. 000 para Root(00) top(01) / 00: 02: 308 para Root(00) para top(01)
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