The 8051 Assembly Language Overview Data transfer instructions

The 8051 Assembly Language

Overview • • Data transfer instructions Addressing modes Data processing (arithmetic and logic) Program flow instructions

Data Transfer Instructions • MOV dest, source • Stack instructions PUSH byte POP byte dest source ; increment stack ; move byte ; move from stack ; decrement pointer, on stack to byte, stack pointer • Exchange instructions XCH a, byte XCHD a, byte ; exchange accumulator and byte ; exchange low nibbles of ; accumulator and byte

Addressing Modes Immediate Mode – specify data by its value mov A, #0 ; put 0 in the accumulator ; A = 0000 mov R 4, #11 h ; put 11 hex in the R 4 register ; R 4 = 0001 mov B, #11 ; put 11 decimal in b register ; B = 00001011 mov DPTR, #7521 h ; put 7521 hex in DPTR ; DPTR = 0111010100100001

Addressing Modes Immediate Mode – continue MOV DPTR, #7521 h MOV DPL, #21 H MOV DPH, #75 COUNT EGU 30 ~ ~ mov R 4, #COUNT MOV DPTR, #MYDATA ~ ~ 0 RG 200 H MYDATA: DB “IRAN”

Addressing Modes Register Addressing – either source or destination is one of CPU register MOV R 0, A MOV ADD MOV MOV A, R 7 A, R 4 A, R 7 DPTR, #25 F 5 H R 5, DPL R, DPH Note that MOV R 4, R 7 is incorrect

Addressing Modes Direct Mode – specify data by its 8 -bit address Usually for 30 h-7 Fh of RAM Mov Mov a, 70 h R 0, 40 h 56 h, a 0 D 0 h, a ; copy contents of RAM at 70 h to a ; put contents of a at 56 h to a ; put contents of a into PSW

Addressing Modes Direct Mode – play with R 0 -R 7 by direct address MOV A, 4 MOV A, R 4 MOV A, 7 MOV A, R 7 MOV 7, 2 MOV R 7, R 6 MOV R 2, #5 MOV R 2, 5 ; Put 5 in R 2 ; Put content of RAM at 5 in R 2

Addressing Modes Register Indirect – the address of the source or destination is specified in registers Uses registers R 0 or R 1 for 8 -bit address: mov psw, #0 mov r 0, #0 x 3 C mov @r 0, #3 ; use register bank 0 ; memory at 3 C gets #3 ; M[3 C] 3 Uses DPTR register for 16 -bit addresses: mov dptr, #0 x 9000 movx a, @dptr ; dptr 9000 h ; a M[9000] Note that 9000 is an address in external memory

Use Register Indirect to access upper RAM block (+8052)

Addressing Modes Register Indexed Mode – source or destination address is the sum of the base address and the accumulator(Index) • Base address can be DPTR or PC mov dptr, #4000 h mov a, #5 movc a, @a + dptr ; a M[4005]

Addressing Modes Register Indexed Mode continue • Base address can be DPTR or PC ORG 1000 h PC • • 1000 1002 1003 mov a, #5 movc a, @a + PC Nop ; a M[1008] Table Lookup MOVC only can read internal code memory

Acc Register • A register can be accessed by direct and register mode • This 3 instruction has same function with different code 0703 E 500 0705 8500 E 0 0708 8500 E 0 mov a, 00 h mov acc, 00 h mov 0 e 0 h, 00 h • Also this 3 instruction 070 B E 9 070 C 89 E 0 070 E 89 E 0 mov a, r 1 mov acc, r 1 mov 0 e 0 h, r 1

SFRs Address • B – always direct mode - except in MUL & DIV 0703 8500 F 0 0706 8500 F 0 mov b, 00 h mov 0 f 0 h, 00 h 0709 8 CF 0 070 B 8 CF 0 mov b, r 4 mov 0 f 0 h, r 4 • P 0~P 3 – are direct address 0704 F 580 0706 F 580 0708 859080 mov p 0, a mov 80 h, a mov p 0, p 1 • Also other SFRs (pcon, tmod, psw, …. )

SFRs Address All SFRs such as (ACC, B, PCON, TMOD, PSW, P 0~P 3, …) are accessible by name and direct address But both of them Must be coded as direct address

8051 Instruction Format • immediate addressing Op code add a, #3 dh Immediate data ; machine code=243 d • Direct addressing Op code mov r 3, 0 E 8 h Direct address ; machine code=ABE 8

8051 Instruction Format • Register addressing Op. E 8 code 070 D 070 E 070 F 0710 0711 0712 0713 0714 0715 0716 0717 E 9 EA ED EF 2 F F 8 F 9 FA FD FD n na, r 0 n mov mov mov add mov mov mov a, r 1 a, r 2 a, r 5 a, r 7 r 0, a r 1, a r 2, a r 5, a ; E 8 ; E 9 ; EA ; ED ; Ef = = = 1110 1110 1001 1010 1101 1111

8051 Instruction Format • Register indirect addressing Op code mov a, @Ri 070 D 070 E 070 F 0710 0711 0712 E 7 93 83 E 0 F 2 E 3 i ; i = 0 or 1 movc movx movx a, @r 1 a, @a+dptr a, @a+pc a, @dptr, a @r 0, a a, @r 1

8051 Instruction Format • relative addressing Op code Relative address here: sjmp here ; machine code=80 FE(FE=-2) Range = (-128 ~ 127) • Absolute addressing (limited in 2 k current mem block) A 10 -A 8 0700 0702 0703 0704 0705 E 106 00 00 Op code 1 2 3 4 5 6 7 8 A 7 -A 0 org 0700 h ajmp next nop nop next: end 07 FEh ; next=706 h

8051 Instruction Format • Long distance address A 15 -A 8 Op code A 7 -A 0 Range = (0000 h ~ FFFFh) 0700 0703 0704 0705 0706 020707 00 00 1 2 3 4 5 6 7 8 org 0700 h ajmp next nop nop next: end ; next=0707 h

Stacks push pop stack pointer stack Go do the stack exercise…. .

Stack • Stack-oriented data transfer – Only one operand (direct addressing) – SP is other operand – register indirect - implied • Direct addressing mode must be used in Push and Pop mov sp, #0 x 40 push 0 x 55 pop b ; ; Initialize SP SP SP+1, M[SP] M[55] M[41] M[55] b M[55] Note: can only specify RAM or SFRs (direct mode) to push or pop. Therefore, to push/pop the accumulator, must use acc, not a

Stack (push, pop) • Therefore Push push Push Pop Push Pop a r 0 r 1 acc psw b 13 h 0 1 7 8 0 e 0 h 0 f 0 h ; is ; is invalid correct ; acc ; b

Exchange Instructions two way data transfer XCH a, 30 h XCH a, R 0 XCH a, @R 0 XCHD a, R 0 a[7. . 4] a[3. . 0] ; a M[30] ; a R 0 ; a M[R 0] ; exchange “digit” R 0[7. . 4] R 0[3. . 0] Only 4 bits exchanged

Bit-Oriented Data Transfer • transfers between individual bits. • Carry flag (C) (bit 7 in the PSW) is used as a single-bit accumulator • RAM bits in addresses 20 -2 F are bit addressable mov C, P 0. 0 mov C, 67 h mov C, 2 ch. 7

SFRs that are Bit Addressable SFRs with addresses ending in 0 or 8 are bit-addressable. (80, 88, 90, 98, etc) Notice that all 4 parallel I/O ports are bit addressable.