TH Resynthesis for Reliability Design ShihChieh Chang Department

  • Slides: 55
Download presentation
TH Re-synthesis for Reliability Design Shih-Chieh Chang Department of Computer Science National Tsing Hua

TH Re-synthesis for Reliability Design Shih-Chieh Chang Department of Computer Science National Tsing Hua University NTHU-CS VLSI/CAD LAB 1 EDA

Reliability Design · Logic Re-synthesis for delay variation tolerance (DAC 04) · A Vectorless

Reliability Design · Logic Re-synthesis for delay variation tolerance (DAC 04) · A Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuits (ICCAD 04) 2

Reliability Design · Logic Re-synthesis for delay variation tolerance (DAC 04) · A Vectorless

Reliability Design · Logic Re-synthesis for delay variation tolerance (DAC 04) · A Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuits (ICCAD 04) 3

Delay Variation Problem · Circuit delay is increasingly sensitive to - process variation -

Delay Variation Problem · Circuit delay is increasingly sensitive to - process variation - delay defects - IR drop, cross talk · Timing violation due to delay variation. 4

Pessimistic Delay Analysis · Traditional solutions: Delay variation problem is alleviated by adding timing

Pessimistic Delay Analysis · Traditional solutions: Delay variation problem is alleviated by adding timing margin. - Unnecessary pessimism: a fabricated ASIC may run up to 40% faster [Chinnery and Keutzer]. - Adding timing margin may not be possible. · Our solutions: Add redundancy (area penalty) for delay variation tolerance. 5

Delay Variation on a Gate · Gates along critical paths are vulnerable to delay

Delay Variation on a Gate · Gates along critical paths are vulnerable to delay variation. · Vulnerable gates have small slacks. Gate delay = 1 2 Circuit delay = 6 6 7

Delay Tolerance and Slack · A gate’s slack: the delay increase without violating circuit’s

Delay Tolerance and Slack · A gate’s slack: the delay increase without violating circuit’s delay. · Slack has correlation with delay tolerance - Smaller slack more vulnerable. - Increase slacks of gates increase delay variation tolerance. 7

Delay Tolerance on a Circuit · Definition: A circuit has dt delay tolerance if

Delay Tolerance on a Circuit · Definition: A circuit has dt delay tolerance if the smallest slack is dt. • gate delay = 1 • timing requirement = 7 8

Delay Tolerance on a Circuit · Definition: A circuit has dt delay tolerance if

Delay Tolerance on a Circuit · Definition: A circuit has dt delay tolerance if the smallest slack is dt. The smallest slack is 1 The circuit has 1 delay tolerance 1 1 1 9 1

Problem Formulation · Inputs: - a circuit and, - a delay tolerance requirement dt,

Problem Formulation · Inputs: - a circuit and, - a delay tolerance requirement dt, · Outputs: - a re-synthesized circuit with dt delay tolerance. 10

Our Basic Idea · Add redundant gates so that the smallest slack is increased.

Our Basic Idea · Add redundant gates so that the smallest slack is increased. Now: 1 delay tolerance Goal: 2 delay tolerance 1 1 1 1 V voting machine 11

Our Basic Idea · Function does not change, but the smallest slack is increased

Our Basic Idea · Function does not change, but the smallest slack is increased to 2. The circuit has 2 delay tolerance 2 2 2 V voting machine 12

Steps of our approach · Start with Triple modular redundancy: three copies and a

Steps of our approach · Start with Triple modular redundancy: three copies and a voting machine. V Voting machine 13

Property of TMR (1) · Any two copies correct output correct · Each wire/gate

Property of TMR (1) · Any two copies correct output correct · Each wire/gate is redundant. 1 1 1 14 0 V 1 Voting machine 1

Property of TMR (2) · The delay is NOT decided by the latest signal.

Property of TMR (2) · The delay is NOT decided by the latest signal. The second arriving signal V The latest signal 15

Property of TMR (2) · If a node’s delay becomes infinity, it will not

Property of TMR (2) · If a node’s delay becomes infinity, it will not affect the final delay. · Each wire/gate has infinite slack in a TMR. V Delay = infinite 16

TMR v. s. Delay Tolerance · TMR can tolerate delay variation due to infinite

TMR v. s. Delay Tolerance · TMR can tolerate delay variation due to infinite slack. · Process variation or noises may cause circuit delay to increase by 10% - 20%. Infinite slack is over-protective. · 200% area penalty in a TMR is impractical. 17

Slack Changes After Wire Removal Gate slack = infinite 0 V 18

Slack Changes After Wire Removal Gate slack = infinite 0 V 18

Removing Redundant Wires · After removing a redundant wire/gate, - circuit function does not

Removing Redundant Wires · After removing a redundant wire/gate, - circuit function does not change, - some slacks may be decreased. · Objective: remove redundant wires/gates while maintaining the smallest slack dt. 19

Removing Wires V 20

Removing Wires V 20

Removing Wires The smallest slack is 2 Satisfy dt=2 V 21

Removing Wires The smallest slack is 2 Satisfy dt=2 V 21

Signal Sharing · Share the functions of side-input wires. V 22

Signal Sharing · Share the functions of side-input wires. V 22

Signal Sharing · Share the functions of side-input wires. V 23

Signal Sharing · Share the functions of side-input wires. V 23

Resulting Circuit The smallest slack is 2 Satisfy dt=2 V 24

Resulting Circuit The smallest slack is 2 Satisfy dt=2 V 24

Outline · Delay variation problem · Triple Modular Redundancy (TMR) · Re-synthesis for delay

Outline · Delay variation problem · Triple Modular Redundancy (TMR) · Re-synthesis for delay variation tolerance · Experimental results · Conclusion 25

Experimental Flow · Given a circuit, optimize the circuit by script. delay and obtain

Experimental Flow · Given a circuit, optimize the circuit by script. delay and obtain the circuit’s delay. · Re-synthesize the circuit using dt = 10% * the circuit’s delay or 15% * the circuit’s delay 26

Experimental Results Original Circuit Delay dt=10% Overhead (%) dt=15% Delay Overhead (%) Delay Apex

Experimental Results Original Circuit Delay dt=10% Overhead (%) dt=15% Delay Overhead (%) Delay Apex 6 11. 6 16. 4 11. 2 23. 7 11. 4 Apex 7 11. 4 12. 6 11. 2 38. 2 11. 4 Frg 1 11. 8 18. 9 10. 8 34. 3 11. 5 Pair 14. 4 17. 2 14. 0 23. 5 13. 8 S 344 12. 3 12. 2 11. 8 38. 3 11. 3 S 349 12. 8 22. 0 12. 2 50. 3 12. 0 S 526 8. 9 19. 1 8. 8 70. 3 8. 9 S 641 12. 9 15. 2 12. 4 17. 4 11. 7 S 713 12. 9 12. 6 12. 3 17. 9 11. 9 S 1488 13. 1 39. 2 12. 7 69. 9 13. 2 Avg. 20. 8 27 40. 6

Statistical Analysis · Compare the statistically timing between a circuit and its re-synthesized circuit.

Statistical Analysis · Compare the statistically timing between a circuit and its re-synthesized circuit. · Assume each gate’s delay to be a probability density function as described in [Liou DAC 02]. · Run Monte-Carlo to generate 10, 000 samples for both a circuit and its re-synthesized circuit. · Count the number of samples whose delay satisfies a pre-defined delay requirement. · Delay requirement = 1. 128 * the circuit’s delay

Experimental Results Circuit Timing requirement Statistic Analysis Original dt=10% Apex 6 12. 7 4062

Experimental Results Circuit Timing requirement Statistic Analysis Original dt=10% Apex 6 12. 7 4062 7929 Apex 7 12. 5 8820 9924 Frg 1 12. 9 8361 9081 Pair 15. 8 6192 8775 S 344 13. 5 8247 8835 S 349 14. 0 7812 8565 S 526 9. 8 6759 8460 S 641 14. 2 9078 9765 S 713 14. 2 8319 8412 S 1488 14. 3 6933 9990 1 1. 28 Avg. 29

Conclusion · Re-synthesize for dt delay tolerance. · Adopt wire removal and signal sharing

Conclusion · Re-synthesize for dt delay tolerance. · Adopt wire removal and signal sharing to reduce area overhead. · Area penalty is about 21% for 10% delay tolerance. 30

Reliability Design · Logic Re-synthesis for delay variation tolerance (DAC 04) · A Vectorless

Reliability Design · Logic Re-synthesis for delay variation tolerance (DAC 04) · A Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuits (ICCAD 04) 31

Power Noises · Excessively large current through power bus may cause IR drop and

Power Noises · Excessively large current through power bus may cause IR drop and EM. · Severe IR drop and EM degrade the performance and reliability. · Accurate estimation of Maximum Instantaneous Current (MIC) to analyze noises. 32

Maximum Instantaneous Current 0 0 t=3 t=2 Maximumt=1 current=3 at time t=3 Maximum current=4

Maximum Instantaneous Current 0 0 t=3 t=2 Maximumt=1 current=3 at time t=3 Maximum current=4 at time t=1. · Maximum Instantaneous Current (MIC) - Input vectors and time. 33

Previous Work · Vector dependent: -Find a vector pair -Lower bound estimation · Vector

Previous Work · Vector dependent: -Find a vector pair -Lower bound estimation · Vector Independent: -Not find the worst case vectors -Upper bound estimation -i. Max and PIE [H. Kriplani et al. ] 34

Outline · Maximum instantaneous current (MIC) problem · Signal correlation problems · MIC estimation

Outline · Maximum instantaneous current (MIC) problem · Signal correlation problems · MIC estimation based on the concept of mutual exclusive switching · Experimental results & conclusion 35

Summary · Identifying signal correlation is important for MIC estimation. No correlation ? Correlation

Summary · Identifying signal correlation is important for MIC estimation. No correlation ? Correlation · Contribution: Efficiently identify complex combinational and sequential correlations. 36

Combinational Correlation · Signal correlation in a combinational circuit. The two transitions cannot occur

Combinational Correlation · Signal correlation in a combinational circuit. The two transitions cannot occur simultaneously 37

Combinational Correlation · Can efficiently recognize complicated combinational correlations. t=4 38 Cannot occur simultaneously

Combinational Correlation · Can efficiently recognize complicated combinational correlations. t=4 38 Cannot occur simultaneously

Sequential Correlation · Correlation across sequential elements. t=0 t=1 (0, 1) (f 1, f

Sequential Correlation · Correlation across sequential elements. t=0 t=1 (0, 1) (f 1, f 2)= (0, 0) (1, 1) f 2 f 1 39

Sequential Correlation · Some (next) states are not reachable from a current state. ·

Sequential Correlation · Some (next) states are not reachable from a current state. · Deriving state transition diagram is NOT practical. · Implicitly obtain sequential correlation without the need of state transition diagram. · None of the previous work can detect sequential correlation. 40

Before Exploring Signal Correlation… · Decide whether a set of gates can switch simultaneously

Before Exploring Signal Correlation… · Decide whether a set of gates can switch simultaneously at time=t 1. · Goal: Find necessary conditions for a gate to switch at time=t 1. 41

An Example for MES Detection Mutually Exclusive Switching at t=4 ? 42

An Example for MES Detection Mutually Exclusive Switching at t=4 ? 42

Conflicts Mutually Exclusive Switching Switch at t =4 0 0 Switch at t =4

Conflicts Mutually Exclusive Switching Switch at t =4 0 0 Switch at t =4 1 1 01 0 0 1 Initial values Stable values 43

Conflicts Mutually Exclusive Switching at t=4 44

Conflicts Mutually Exclusive Switching at t=4 44

Necessary Conditions in Sequential Circuits switch at t=2 g Flip-flop 45

Necessary Conditions in Sequential Circuits switch at t=2 g Flip-flop 45

Necessary Conditions in Sequential Circuits · To reveal sequential correlation, we link the two

Necessary Conditions in Sequential Circuits · To reveal sequential correlation, we link the two circuit copies through flip-flops. switch at t=2 0 g g 0 Initial values 0 Flip-flop 46 Stable values

MIC Estimation Based on MES · Use an undirected graph to present the MES

MIC Estimation Based on MES · Use an undirected graph to present the MES relation. · Find a set of nodes that have no edge in between. Switch simultaneously. MES Current contribution =1 Maximum current =3 at time=t 1 MES relation at time=t 1 47

Experimental Flow · Combinational and sequential MCNC ISCAS benchmarks. · Upper bound estimations: i.

Experimental Flow · Combinational and sequential MCNC ISCAS benchmarks. · Upper bound estimations: i. Max, PIE (1000 s_nodes) , and MES. · Lower bound estimations: Random simulation for 3 days. 48

Results for Combinational Circuits i. Max PIE i. Max=2. 6 PIE=2. 3 Random=0. 95

Results for Combinational Circuits i. Max PIE i. Max=2. 6 PIE=2. 3 Random=0. 95 49 Random i. Max=2. 3 PIE=1. 7

Results for Sequential Circuits i. Max PIE Random i. Max=3. 1 PIE=2. 3 50

Results for Sequential Circuits i. Max PIE Random i. Max=3. 1 PIE=2. 3 50

Upper Bound Estimation · Our method derives tighter upper bound for sequential circuits. i.

Upper Bound Estimation · Our method derives tighter upper bound for sequential circuits. i. Max=2. 3 PIE=1. 7 PIE Avg. MIC 51 i. Max=3. 1 PIE=2. 3

Lower Bound Estimation · If an upper bound is close to the corresponding lower

Lower Bound Estimation · If an upper bound is close to the corresponding lower bound, both estimations are accurate. · For small circuits, our upper bound results are close to the lower bound results. · For large circuits, random simulation may only reach small portion of solution space. Ex. In s 344, only 57% of 2625 reachable states. 52

Run Time · The run time for i. Max takes few seconds for the

Run Time · The run time for i. Max takes few seconds for the largest circuit. · Our run time is in general faster than that of PIE. · The MIC estimation is performed only one time and our run time is reasonable for a large design. Ex. In s 15850, ours=2500 sec. ; PIE=15000 sec. 53

Conclusion · A vectorless method to estimate the MIC for sequential circuits. · Based

Conclusion · A vectorless method to estimate the MIC for sequential circuits. · Based no mutually exclusive switching. · Experimental results on sequential circuits are encouraging. 54

Thank you! 55

Thank you! 55