TH A Probabilistic Approach to Logic Equivalence Checking

TH A Probabilistic Approach to Logic Equivalence Checking Chun-Yao Wang (王俊堯) Dept. CS NTHU 2006. 01. 06 NTHU-CS VLSI/CAD LAB 1 EDA

Outline • Introduction • Previous Work • Probabilistic Logic Equivalence Checking – Exact Approach – Approximate Approach • Experimental Results • Conclusions NTHU-CS VLSI/CAD LAB 2 TH EDA

Motivation • Logic equivalence checking – Logic optimization, scan insertion, manual modification • Exhaustively simulation is infeasible for practical designs NTHU-CS VLSI/CAD LAB 3 TH EDA

Problem Formulation • Given two netlists N_ori, N_opt – N_ori is the original netlist – N_opt is the netlist after area/timing optimization (restructuring) • The problem is to formally verify the equivalence of N_ori and N_opt NTHU-CS VLSI/CAD LAB 4 TH EDA

Outline • Introduction • Previous Work • Probabilistic Logic Equivalence Checking – Exact Approach – Approximation Approach • Experimental Results • Conclusions NTHU-CS VLSI/CAD LAB 5 TH EDA

Previous Work (1/3) • Probabilistic based approach – Assume circuits only consist of AND/OR/NOT gates – Probability formulae (independent signals) • Symbol represents the probability of signal one a a 1 -a a b b a 1 - (1 - a) (1 - b) = a + b - a b b NTHU-CS VLSI/CAD LAB 6 TH EDA

Previous Work (2/3) • Assign the probability symbol to PIs • Derive probability expressions • Perform exponent suppression ( xm→ x ) on reconvergent gates • Compare the output probabilities (unique) • Problem: Representation complexity a b a × (1 -b) + b × c – a × (1 -b) × b × c = a × (1 -b) + b × c – a × (b-b 2) × c = a × (1 -b) + b × c – a × (b-b) × c = a × (1 -b) + b × c 1 -b c b×c E. J. Mc. Cluskey et al, "Probabilistic treatment of general combinational networks, " IEEE Trans. Computer, June 1975 NTHU-CS VLSI/CAD LAB 7 TH EDA

Previous Work (3/3) • Assign real numbers as input probabilities instead of symbols – Evaluate output probability (number) of circuits • Arithmetic operations – Problems: • Aliasing occurrence • Signal correlation J. A. Abraham et al, " Probabilistic design verification , " ICCAD, 1991 NTHU-CS VLSI/CAD LAB 8 TH EDA

Aliasing Problem • Two different circuits have the same output probability • Example: – N 1≡N 2, but with the same output probability N 1 N 2 • Multiple runs increase the confidence level NTHU-CS VLSI/CAD LAB 9 TH EDA

Signal Correlation Problem • Numbers cannot be assigned immediately – Numbers should be assigned after exponent suppression • Example: – Two inputs of G 2 are correlated with signal B – Without considering exponent suppression – Considering exponent suppression ( A B G 1 ×) G 2 (○) NTHU-CS VLSI/CAD LAB 10 TH EDA

Outline • Introduction • Previous Work • Probabilistic Logic Equivalence Checking – Exact Approach • • Aliasing-Free Probability Assignments Encoding Scheme and Alternative Operations Dealing with Signal Correlation Internal Tree-Structure Replacement – Approximate Approach • Experimental Results • Conclusions NTHU-CS VLSI/CAD LAB 11 TH EDA

Aliasing-Free Probability Assignments • An aliasing-free assignment – xi= – ai+1=(ai-1)2+1, a 1>=3 & Z+, i=1~n-1 – Problem: • The assignments grow exponentially • n <= 24 is feasible • Examples: – x 1 = , x 2 = , x 3 = , …, x 6 = , … Teslenko, M. , Dubrova, E. , and Tenhunen H. , "Computing a perfect input assignment for probabilistic verification", EMT'2005, May 12 -15 NTHU-CS VLSI/CAD LAB 12 TH EDA

Why Aliasing-Free • A 3 -input function has – Assume x 1 = , x 2 = distinct functions , x 3 = – The probability of each function is distributed from ~ X 1 X 2 00 X 3 10 01 11 0 1 NTHU-CS VLSI/CAD LAB 13 TH EDA

Encoding Scheme • Denominators are either ai or the product of ai – , , • Suppose the weight of bit-i is ai – Multiplication replaces addition – Reduce memory usage • Examples: – x 1 = = = – x 2 = = = – x 3 = = = – x 1 × x 2 × x 3 = NTHU-CS VLSI/CAD LAB × × = ( 14 ) TH EDA

Example – AND Gate • Original formulation • Bitwise-AND (∩) operation ( )= ( ) NTHU-CS VLSI/CAD LAB ( ) 15 TH EDA

Shift-Add Operation • When transforming two input probabilities to their equivalent probabilities – Denominators are either 3, 5, 17, …, – Shift-add operations are used to obtain the numerator instead of multiplication operations • Example: – ( )= ( ) – Numerator 5 = 1 × 5 can be obtained by ( 0001 << 2 ) + 0001 = 0101 = 5 NTHU-CS VLSI/CAD LAB 16 TH EDA

Example – OR Gate • Original formulation • Bitwise-OR (∪) operation ( )= ( ) NTHU-CS VLSI/CAD LAB ( ) 17 TH EDA

Dealing with Signal Correlation • When transforming two input probabilities to their equivalent probabilities – The lowest common multiple suppresses the correlation of two input probabilities if the denominators have the same factor A B ( )= ( ) G 1 ( ) G 3 C G 2 NTHU-CS VLSI/CAD LAB ( )= ( ) 18 TH EDA

Internal Tree-Structure Replacement • Example: – Verify if N 1≡ N 2 – Only two input assignments A B and A B G 1 are used G 1 G 2 C C N 1 NTHU-CS VLSI/CAD LAB ≡ N 2 19 TH EDA

Outline • Introduction • Previous Work • Probabilistic Logic Equivalence Checking – Exact Approach • • Aliasing-Free Probability Assignments Encoding Scheme and Alternative Operations Dealing with Signal Correlation Internal Tree-Structure Replacement – Approximate Approach • Experimental Results • Conclusions NTHU-CS VLSI/CAD LAB 20 TH EDA

Approximation Structure • • • Connect Random Probability Generator (RPG) to DUV Aliasing-free assignments are assigned to RPG’s PIs RPG produces every possible function |PO| in RPG = |PI| in DUV Verify the equivalence of S 1 and S 2 Verify the equivalence of L 1 and L 2 L 1 aliasing-free assignments ︰ R P G NTHU-CS VLSI/CAD LAB : L 2 aliasing-free assignments S 1 21 ︰ R P G ︰ S 2 TH EDA

Problem Formulation • Given two large netlists S 1, S 2 (# of required input assignments > 24) • The problem is to verify the equivalence of S 1 and S 2 with aliasing rate (ε) • ε pr(S 1 S 2 ∩ L 1 L 2) NTHU-CS VLSI/CAD LAB 22 TH EDA

Analysis (1/3) • Assume r (resource) input assignments are available, and S 1, S 2 (DUVs) have n PIs. What is the aliasing rate ε in using Approximation Structure to verify the equivalence of S 1 and S 2? L 1 aliasing-free Assignments ︰ R P G r NTHU-CS VLSI/CAD LAB : L 2 aliasing-free assignments S 1 r n 23 ︰ R P G ︰ S 2 n TH EDA

Analysis (2/3) L 1 2/15 1/3 1/5 R P G 7/15 9/15 S 1 • r=2, n=3, connect 2/15, 7/15, 9/15 to the inputs of S 1 • Uniformly hash 16 S-functions to one L-function • ε NTHU-CS VLSI/CAD LAB 24 L_0 S_0~S_15 L_1 S_16~S_31 L_2 S_32~S_47 L_3 S_48~S_63 L_4 S_64~S_79 L_5 S_80~S_95 L_6 S_96~S_111 L_7 S_112~S_127 L_8 S_128~S_143 L_9 S_144~S_159 L_10 S_160~S_175 L_11 S_176~S_191 L_12 S_192~S_207 L_13 S_208~S_223 L_14 S_224~S_239 L_15 S_240~S_255 TH EDA

Analysis (3/3) • ε pr(S 1 ≠ S 2 ∩ L 1 = L 2) = pr(L 1 = L 2) - pr(S 1 = S 2) = • Assume n>24 ( – – – ), εis simply related to r r=8, ε 10 -77 r=9, ε 10 -154 r=10, ε 10 -308 r=11, ε 10 -616 r=12, ε 10 -1233 NTHU-CS VLSI/CAD LAB - S 1=S 2 25 L 1=L 2 TH EDA

Outline • Introduction • Previous Work • Probabilistic Logic Equivalence Checking – Exact Approach – Approximate Approach • Experimental Results • Conclusions NTHU-CS VLSI/CAD LAB 26 TH EDA

Experimental Results – exact approach Time (s) Ours / BDD Mem. (MB) Ours / BDD N 0. 76 / 0. 66 6. 66 / 6. 45 15 / 15 Y 0. 22 / 0. 22 5. 48 / 5. 57 6 7 / 32 Y 0. 05 / 0. 05 3. 41 / 4. 80 133 66 19 / 19 Y 0. 17 / 0. 23 5. 62 / 5. 30 i 8 133 81 17 / 17 Y 1. 71 / 1. 44 11. 00 / 10. 00 apex 6 135 99 22 / 24 Y 0. 51 / 0. 42 9. 50 / 6. 23 x 3 135 99 23 / 24 Y 1. 41 / 0. 45 15. 00 / 6. 52 i 6 138 67 5/5 N 0. 21 / 0. 32 5. 87 / 5. 94 frg 2 143 139 23 / 25 Y 2. 35 / 0. 87 15. 00 / 7. 63 i 7 199 67 6/6 N 0. 25 / 0. 46 6. 25 / 6. 33 des 256 245 18 / 19 Y 5. 23 / 4. 42 15. 00 / 15. 00 Circuits |PI| |PO| i 9 88 63 13 / 13 x 4 94 71 i 3 132 i 5 NTHU-CS VLSI/CAD LAB Max ai / Max TFI|PI| Tree (Y/N) 27 TH EDA

Experimental Results – approximate approach (r=10, ε 10 -308) Circuits |PI| |PO| n=Max TFI|PI| RPG |PO| Time (s) Mem. (MB) C 432 36 7 36 6 0. 32 7. 39 C 499 41 32 1. 71 6. 27 C 880 60 26 45 9 0. 26 5. 16 C 1355 41 32 2. 21 6. 96 C 1908 33 25 1. 37 6. 64 C 2670 233 140 122 10 1. 15 8. 52 C 3540 50 22 50 17 4. 69 9. 38 C 5315 178 123 67 66 0. 25 8. 34 C 6288 32 32 32 21 29. 41 18. 00 C 7552 207 108 194 46 3. 71 11. 00 NTHU-CS VLSI/CAD LAB 28 TH EDA

Outline • Introduction • Previous Work • Probabilistic Logic Equivalence Checking – Exact Approach – Approximate Approach • Experimental Results • Conclusions NTHU-CS VLSI/CAD LAB 29 TH EDA

Conclusions • An aliasing-free assignment procedure is proposed • More efficient operations, such as bitwise-AND, bitwise-OR, and shift-add operations are used • The aliasing-free assignment and bitwise operations deal with the signal correlation problem well • Internal tree-structure replacement is used to reduce the number of required input assignments • An approximate approach with configurable aliasing rate is proposed for large circuits NTHU-CS VLSI/CAD LAB 30 TH EDA

Appendix • P. 31~P. 37 NTHU-CS VLSI/CAD LAB 31 TH EDA

Calculate Signal Probability • Transform two input probabilities to their equivalent probability – The denominator is the lowest common multiple of the original denominators • The two new numerators conduct bitwise-AND/ bitwise-OR operation to obtain the numerator of output probability if it is an AND/OR gates NTHU-CS VLSI/CAD LAB 32 TH EDA

Why Work – AND Gate • The operation 0101∩ 0011 is analogous to perform intersection on minterm sets X 2 X 1 prob. of minterm ( )= ( ) bitwise-AND 0 0 (1 - ) × (1 - ) = 0 0 1 (1 - ) × = 1 0 0 1 0 × (1 - ) = 0 2 1 1 × 1 NTHU-CS VLSI/CAD LAB = ( ) 33 ∩ 1 1 = 0 1 TH EDA

Why Work – OR Gate • The operation 10001∪ 00101 is analogous to perform union on minterm sets X 2 X 1 prob. of minterm 0 0 (1 - 0 1 (1 - ) × (1 - ) = )× = ( ) ( )= ( ) bitwise-OR 0 0 0 1 1 1 1 0 × (1 - ) = ∪ = 0 1 1 2 1 1 × 1 NTHU-CS VLSI/CAD LAB = ( ) 34 TH EDA

Internal Tree-Structure Replacement (1/2) • Only consider two Boolean networks for verification – Internal tree-structure replacement can be used to reduce the number of required assignments – The output probability is changed, but it does not affect the judgement on the equivalence checking NTHU-CS VLSI/CAD LAB 35 TH EDA

Analysis (2/3) • pr(S 1 = S 2) = • pr(L 1 = L 2) = • If S 1=S 2, then L 1=L 2 – (1) pr(S 1 = S 2 ∩ L 1 ≠ L 2) = 0 • pr(S 1 = S 2 ∩ L 1 = L 2) + pr(S 1 = S 2 ∩ L 1 ≠ L 2) = pr(S 1 = S 2) = – (2) pr(S 1 = S 2 ∩ L 1 = L 2) = • (3) ε pr(S 1 ≠ S 2 ∩ L 1 = L 2) = pr(L 1 = L 2) - pr(S 1 = S 2) = • (4) pr(S 1 ≠ S 2 ∩ L 1 ≠ L 2) = 1 – pr(L 1 = L 2) = 1 • (1) + (2) + (3) + (4) = 1 S 1=S 2 NTHU-CS VLSI/CAD LAB L 1=L 2 36 - L 1=L 2 TH EDA

Experimental Setup • Benchmarks – n<=24 exact approach MCNC benchmarks in BLIF format – n>24 approximate approach ISCAS-85 benchmarks in BLIF format • Environment – SIS environment – Sun Blade 2500 workstation • Experimental flow – Map benchmarks to the SIS library (22 -1. genlib), decompose the networks to AND/OR/NOT gates – Verify the equivalence between original Netlist and Netlist after area optimization (map –m 0) – Separate multiple-output network into many single-output subnetworks – BDD based approach - ntbdd_verify_network( N 1, N 2, DFS_ORDER, ONE_AT_A_TIME ) NTHU-CS VLSI/CAD LAB 37 TH EDA