Testing Analog Digital Products Dr Vishwani D Agrawal

Testing Analog & Digital Products Lecture 1: Introduction n n n VLSI realization process

VLSI Realization Process Customer’s need Determine requirements Write specifications Design synthesis and Verification Test

Definitions n n n Design synthesis: Given an I/O function, develop a procedure to

Verification vs. Test n n Verification Verifies correctness of design. Performed by simulation, hardware

Problems of Ideal Tests n n Ideal tests detect all defects produced in the

Real Tests n n Based on analyzable fault models, which may not map on

Testing as Filter Process Good chips Prob(good) = y Fabricated chips Defective chips Prob(bad)

Costs of Testing n n n Design for testability (DFT) Chip area overhead and

Present and Future* 1997 -2001 2003 - 2006 Feature size (micron) Transistors/sq. cm 0.

Design for Testability (DFT) DFT refers to hardware design styles or added hardware that

Cost of Manufacturing Testing in 2000 AD n n n 0. 5 -1. 0

Roles of Testing n n Detection: Determination whether or not the device under test

A Modern VLSI Device System-on-a-chip (SOC) Data terminal Copyright 2001, Agrawal & Bushnell DSP

Course Outline Part I: Introduction n n Basic concepts and definitions Yield and product

Course Outline (Cont. ) Part II: Test Methods n n n n Logic and

Course Outline (Cont. ) Part III: DFT n n n Scan design Built-in self-test

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Testing Analog & Digital Products Dr. Vishwani D. Agrawal James J. Danaher Professor of Electrical and Computer Engineering Auburn University, Alabama 36849, USA vagrawal@eng. auburn. edu http: //www. eng. auburn. edu/~vagrawal July 12 – 13, 2005 Copyright 2001, Agrawal & Bushnell Day-1 AM-1 Lecture 1 1

Testing Analog & Digital Products Lecture 1: Introduction n n n VLSI realization process Verification and test Ideal and real tests Costs of testing Roles of testing A modern VLSI device - system-on-a-chip Course outline Part I: Introduction to testing (Day-1 AM) Part II: Test methods (Day-1 PM and Day-2 AM) Part III: Design for testability (Day-2 PM) Copyright 2001, Agrawal & Bushnell Day-1 AM-1 Lecture 1 2

VLSI Realization Process Customer’s need Determine requirements Write specifications Design synthesis and Verification Test development Fabrication Manufacturing test Chips to customer Copyright 2001, Agrawal & Bushnell Day-1 AM-1 Lecture 1 3

Definitions n n n Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes. Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect. Copyright 2001, Agrawal & Bushnell Day-1 AM-1 Lecture 1 4

Verification vs. Test n n Verification Verifies correctness of design. Performed by simulation, hardware emulation, or formal methods. Performed once prior to manufacturing. Responsible for quality of design. Copyright 2001, Agrawal & Bushnell n n Test Verifies correctness of manufactured hardware. Two-part process: 1. Test generation: software process executed once during design 2. Test application: electrical tests applied to hardware Test application performed on every manufactured device. Responsible for quality of devices. Day-1 AM-1 Lecture 1 5

Problems of Ideal Tests n n Ideal tests detect all defects produced in the manufacturing process. Ideal tests pass all functionally good devices. Very large numbers and varieties of possible defects need to be tested. Difficult to generate tests for some real defects. Defect-oriented testing is an open problem. Copyright 2001, Agrawal & Bushnell Day-1 AM-1 Lecture 1 6

Real Tests n n Based on analyzable fault models, which may not map on real defects. Incomplete coverage of modeled faults due to high complexity. Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss. Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level. Copyright 2001, Agrawal & Bushnell Day-1 AM-1 Lecture 1 7

Testing as Filter Process Good chips Prob(good) = y Fabricated chips Defective chips Prob(bad) = 1 - y Copyright 2001, Agrawal & Bushnell Prob(pass test) = high Pr w ob (fa il s s a p ( b o Pr lo = ) t s te tes t) =l ow Prob(fail test) = high Day-1 AM-1 Lecture 1 Mostly good chips Tested chips Mostly bad chips 8

Costs of Testing n n n Design for testability (DFT) Chip area overhead and yield reduction Performance overhead Software processes of test Test generation and fault simulation Test programming and debugging Manufacturing test Automatic test equipment (ATE) capital cost Test center operational cost Copyright 2001, Agrawal & Bushnell Day-1 AM-1 Lecture 1 9

Present and Future* 1997 -2001 2003 - 2006 Feature size (micron) Transistors/sq. cm 0. 25 - 0. 15 4 - 10 M 0. 13 - 0. 10 18 - 39 M Pin count Clock rate (MHz) Power (Watts) 100 – 900 200 – 730 1. 2 – 61 160 - 1475 530 - 1100 2 - 96 * SIA Roadmap, IEEE Spectrum, July 1999 Copyright 2001, Agrawal & Bushnell Day-1 AM-1 Lecture 1 10

Design for Testability (DFT) DFT refers to hardware design styles or added hardware that reduces test generation complexity. Motivation: Test generation complexity increases exponentially with the size of the circuit. Example: Test hardware applies tests to blocks A and B and to internal bus; avoids test generation for combined A and B blocks. Int. Primary Logic bus Logic outputs inputs block A block B (PO) (PI) Test input Copyright 2001, Agrawal & Bushnell Test output Day-1 AM-1 Lecture 1 11

Cost of Manufacturing Testing in 2000 AD n n n 0. 5 -1. 0 GHz; analog instruments; 1, 024 digital pins: ATE purchase price = $1. 2 M + 1, 024 x $3, 000 = $4. 272 M Running cost (five-year linear depreciation) = Depreciation + Maintenance + Operation = $0. 854 M + $0. 085 M + $0. 5 M = $1. 439 M/year Test cost (24 hour ATE operation) = $1. 439 M/(365 x 24 x 3, 600) = 4. 5 cents/second Copyright 2001, Agrawal & Bushnell Day-1 AM-1 Lecture 1 12

Roles of Testing n n Detection: Determination whether or not the device under test (DUT) has some fault. Diagnosis: Identification of a specific fault that is present on DUT. Device characterization: Determination and correction of errors in design and/or test procedure. Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT. Copyright 2001, Agrawal & Bushnell Day-1 AM-1 Lecture 1 13

Course Outline Part I: Introduction n n Basic concepts and definitions Yield and product quality Fault modeling Day 1 AM Reference, Chapters 1 – 4: M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000. http: //www. eng. auburn. edu/~vagrawal/BOOK/books. html Copyright 2001, Agrawal & Bushnell Day-1 AM-1 Lecture 1 15

Course Outline (Cont. ) Part II: Test Methods n n n n Logic and fault simulation Testability measures Combinational circuit ATPG Sequential circuit ATPG Memory test Analog test Day 1 PM and Day 2 AM Reference, Chapters 5 – 11: M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000. http: //www. eng. auburn. edu/~vagrawal/BOOK/books. html Copyright 2001, Agrawal & Bushnell Day-1 AM-1 Lecture 1 16

Course Outline (Cont. ) Part III: DFT n n n Scan design Built-in self-test (BIST) Boundary scan and analog test bus System test and core-based design Day 2 PM Reference, Chapters 14 – 18: M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000. http: //www. eng. auburn. edu/~vagrawal/BOOK/books. html Copyright 2001, Agrawal & Bushnell Day-1 AM-1 Lecture 1 17