Team MUX Adam Burton David Moore Mark Colombo

Team MUX Adam Burton David Moore Mark Colombo Daniel Toler

Introduction • Overview • (3) 16 Bit Master-Slave Rising edge registers using transmission gates • ALU comprised of 5 functional blocks – – – Adder/Subtractor And Or Shift Multiplier

Team MUX- ALU Block Output Register Value 16 16 Cout - 1 16 Bit Adder 16 Bit OR B - 16 16 16 Bit AND 16 ` 8 -1 MUX A - 16 16 Bit Multiplier 16 Bit Shift Control - 3 3 3 Out - 16

Adder/Subtractor Bitslice A B Sub. Signal X Y 1 Bit Adder (Mirror) Z Cin To MUX Cout To next bit slice • In our Adder/Subtractor we had two bit slices with different inverting stages. This was so we could take advantage of the inversion property to cut down on the number of inverters in the carry path.

Shifter Bitslice 1 bit shifter (Passgate Logic) A X B 0 B 1 Shift Amount Z 1 Z 2 Z 3 Z 4 Bundled with other Bitslices • We used passgate logic because the reduced output swing was not an issue, and we could save area.

Functionality Plots Pass c 2 c 1 c 0=001 A 0=0>1 Out 0=0>1 CLK A 0 Out 0

AND C 2 c 1 c 0=110 A 0=1>0 B 0=0 Out 0=1>0 Functionality Plots CLK A 0 Out 0 A 0

SUB c 2 c 1 c 0=011 A 0=1 B 0=1 Out 0=0 Functionality Plots CLK A 0, B 0 Out 0

Innovation Sizing Strategy What to size How to size it Design Trade-Offs Arbitrary Function – 16 bit multiplier

Sizing Not on Critical Path Sized to conserve area On Critical Path Sized for Delay Attempted Logical Effort Calculations Result – Tapered Path for reduced delay Optimized further through simulation Buffers between registers and ALU

Trade-Offs Considered Carry Look-ahead Adder Additional area and power Small benefit to delay Supply Voltage Higher Better Delay, More Power Lower Worse Delay, Less Power Decided on Delay due to being squared in metric, used 5 V

Innovation in Multiplier To produce a 16 -bit output, need 8 -bit multiplier Team MUX Multiplier is 16 bits Despite limited output width, offers more flexibility

Multiplier Attributes The multiplier is a basic array-based multiplier. Delay through the multiplier Power consumption of the multiplier

Results Worst case delay analyzed 0 x 7 FFF + 0 x 0001 Caused all bits to flip Period: 7 ns Frequency: 143 MHz

Results Area measurement Counted up widths Excluded buffers and multiplier Width: 4. 2115*10^-3 m

Results Energy calculation Cycle through all functions with alternating input Integrated instantaneous power over period of operation Energy: 2. 3426*10^-9 J

Results Final Metric D^2*A*E Metric: 4. 846*10 -28 s^2*m*J

Conclusion Meets or exceeds all specifications Implements all functions Low metric value Multiplier is a valuable, common function

Questions?