TDR plans for feedbacks Alessandro Drago XIII Super
TDR plans for feedbacks Alessandro Drago XIII Super. B General Meeting Isola d’Elba, 5/30 -6/4 2010
Super. B bunch-by-bunch feedbacks 2. 1 ns bunch 2. 1 ns am D S Comb gen. k c lo r g 250 W a i d longitudinal DPU LP B FPGA 250 W/500 W 16 bit DAC x 12 bit ADC Phase detector x RF (476 MHz) AM a*RF 6*RF Inj. Trigger LAN DPU LP FPGA transverse 16 bit DAC 3*RF x 12 bit ADC Amplitude detector 31. 5 cm 180 0 User trigger Operator interface realtime and offline analysis programs
Super. B bunch-by-bunch feedbacks bunch 2. 1 ns 31. 5 cm Hybrids S DPU Comb gen. 250 W longitudinal DPU LP 250 W/500 W 16 bit DAC LFE x 12 bit ADC Phase detector FPGA x RF (476 MHz) AM a*RF 6*RF Inj. Trigger LAN DPU TFE LP FPGA transverse 16 bit DAC 3*RF x 12 bit ADC Amplitude detector T. Kicker 2. 1 ns Pickup D L. Kicker 180 0 LBE User trigger Operator interface realtime and offline analysis programs
Bunch-by-bunch feedback plans • • Pickup Hybrids Long. FE Tr. FE D. P. U. Long. BE L. kicker T. kicker • Total • • 0. 2 FTE 1 FTE (in house) or 0. 1 FTE (Dimtel) 1 FTE 4 FTE (in house) or 0. 2 FTE (Dimtel) 0. 6 FTE 0. 4 FTE • 7. 8 FTE (in house) or 3. 1 FTE (partial outsourcing)
IP feedback plans • • • Pickup Analog FE D. P. U. Analog BE Kicker • total • • • 0. 2 FTE 0. 4 FTE 0. 6 FTE • 5. 2 FTE
Longitudinal, transverse and IP feedbacks • L&T • 7. 8 FTE (in house) or 3. 1 FTE feedbacks (partial outsourcing) • IP feedback • 5. 2 FTE • TOTAL • 13 FTE (or 8. 3 FTE with partial outsourcing) • LLFR • 3 FTE x 2 years
- Slides: 6