TDC 130 High performance Time to Digital Converter

TDC 130: High performance Time to Digital Converter in 130 nm Christian MESTER 2008 -03 -27

Index Introduction: • What is a TDC and its use • Application example • HPTDC implementation New TDC 130 • Expected resolution • Current state • Architecture • Focus on DLL • Ideas for further improvement of resolution Pico-Second Timing Workshop Chicago, 27 -28 March 2008 Christian Mester christian. mester@cern. ch Physics Department 2

What is a TDC and its use TDCs are used to measure time (intervals) with high precision • Start – stop measurement q Measurement of time interval between two events: start signal – stop signal Start Stop q Used to measure relatively short time intervals with high precision q Like a stop watch used to measure sport competitions • Time tagging q Measure time of occurrence of events with a given time reference Time reference (Clock) Events to be measured (Hit) Time scale (clock) Hits q Used to measure relative occurrence of many events on a defined time scale q Like a normal watch Pico-Second Timing Workshop Chicago, 27 -28 March 2008 Christian Mester christian. mester@cern. ch Physics Department 3

What is a TDC and its use Special needs for high energy physics • Many thousands of channels needed want to use the same time base for many channels • Rate of measurements can be very high • Very high resolution • Triggered mode must be integrated with TDC function: q store measurements during a given interval q extract only those related to an interesting event, signalled by a trigger Pico-Second Timing Workshop Chicago, 27 -28 March 2008 Christian Mester christian. mester@cern. ch Physics Department 4

ALICE Time of Flight (TOF) ≈ speed of light time of flight particle • ≈25 ps resolution • 160 000 channels Pico-Second Timing Workshop Chicago, 27 -28 March 2008 Christian Mester christian. mester@cern. ch Physics Department 5

Current Implementation (HPTDC) • DLL, hit registers, RC delay and PLL implemented as full custom • 0. 25 µm CMOS technology • 6. 5 x 6. 5 mm² • ≈ 1 million transistors • 225 ball grid array package Pico-Second Timing Workshop Chicago, 27 -28 March 2008 Christian Mester christian. mester@cern. ch Physics Department 6

Index Introduction: • What is a TDC and its use • Application example • HPTDC implementation New TDC 130 • Expected resolution • Current state • Architecture • Focus on DLL • Ideas for further improvement of resolution Pico-Second Timing Workshop Chicago, 27 -28 March 2008 Christian Mester christian. mester@cern. ch Physics Department 7

New TDC 130 vs. current HPTDC Current HPTDC New TDC 130 • ≈ 100 ps bin size on 32 channels or ≈ 25 ps bin size on 8 channels • ≈ 25 ps bin size on 32 channels • 780 ps bin size in low resolution mode • ≈ 800 ps bin size in low resolution mode • 102 µs dynamic range (15 bit) • ≈ 840 µs dynamic range (20 bit) (possibly more) • Max. hit rate on channels depend on other channels’ activity • Higher hit rates, channels are independent • Double pulse resolution: 5 ns to 10 ns (depending on mode) • Minimum double pulse resolution ≤ 2 ns • Lower power consumption • Lower cost Pico-Second Timing Workshop Chicago, 27 -28 March 2008 Christian Mester christian. mester@cern. ch Physics Department 8

TDC 130: Current state Timing part To be submitted in May 2008 • PLL • DLL • Hit registers • 24. 4 ps bin size in “ 32” channels • If time allows: additional interpolation function Pico-Second Timing Workshop Chicago, 27 -28 March 2008 Christian Mester christian. mester@cern. ch Physics Department 9

Core architecture of TDC 130 Clock (40 MHz, or 80 MHz) 32 delay elements+dummies Phase detector, Charge pump, Filter PLL 1. 28 GHz 32 Hit[31: 0] LVDS 32 Hit register × 32 Readout Pico-Second Timing Workshop Chicago, 27 -28 March 2008 Christian Mester christian. mester@cern. ch Physics Department 10

DLL Timing part • Phase detector: bang-bang type • Loop filter: Capacitor to ground • Control voltage for dummies is separated using mirrors not to inject noise on the main elements’ control voltage • Not shown: q Differential to single-ended conversion between delay line and phase detector q Differential to single-ended conversion before hit registers and buffers Note that the load seen by each delay element has to be the same. Pico-Second Timing Workshop Chicago, 27 -28 March 2008 Christian Mester christian. mester@cern. ch Physics Department 11

DLL: Delay cell Differential delay elements • With local fine adjustment to compensate mismatch effects This works like an inductor (within a limited frequency range) Local fine adjustment to compensate for mismatch Pico-Second Timing Workshop Chicago, 27 -28 March 2008 Christian Mester christian. mester@cern. ch Physics Department 12

Monte Carlo Simulation: INL/DNL (TDC 130) 25 runs, process variations only VCDL, differential-to-single-ended converters and buffers Pico-Second Timing Workshop Chicago, 27 -28 March 2008 Christian Mester christian. mester@cern. ch Physics Department 13

Monte Carlo Simulation: INL/DNL (TDC 130) 25 runs, mismatch variations only VCDL, differential-to-single-ended converters and buffers Pico-Second Timing Workshop Chicago, 27 -28 March 2008 Christian Mester christian. mester@cern. ch Physics Department 14

Measurement of HPTDC: INL correction Effective RMS resolution: • 40 ps without INL correction • 17 ps with look-up table INL correction (as a fixed 40 MHz pattern has been observed) Measurements from ALICE-TOF Without INL compensation After INL compensation Pico-Second Timing Workshop Chicago, 27 -28 March 2008 Christian Mester christian. mester@cern. ch Physics Department 15

How to improve the resolution? HPTDC’s very high resolution mode: • Interpolation using R-C delay elements and 4 normal channels per very high resolution channel ( only 8 instead of 32 channels available in very high resolution mode) TDC 130: • Interpolation — without reducing the number of channels? • Ideas: q R-C networks: attenuation, low pass: slew rate deteriorates q Transmission lines: potentially long, less attenuation q Delay elements (like in the DLL) – Use a second DLL with slightly less (e. g. 26) delay elements than the main DLL – Let the clock signal propagate in both DLLs – Distribute the second DLL’s control voltage to delay elements in the channels • Interpolation factor 4 ≈6 ps bin size Pico-Second Timing Workshop Chicago, 27 -28 March 2008 Christian Mester christian. mester@cern. ch Physics Department 16

TDC 130: Outlook Final chip • General architecture (channel organization, 1 buffer per channel) fixed • Will support triggered mode • Readout: to be discussed Future of the development • “Client” expectations • “Client” involvement • “Availability” of manpower • “Maintain” expertise Pico-Second Timing Workshop Chicago, 27 -28 March 2008 Christian Mester christian. mester@cern. ch Physics Department 17