TCI CPU Memory Accelerator 1 CPU Accelerator 2

ベースとなる技術①：TCIと ビルディングブロックコンピューティングシステム CPU Memory Accelerator 1 CPU Accelerator 2 Accelerator 1 Memory Accelerator 2 CPU Accelerator 1 Accelerator 2 1 step: Various Combination can be done after chip-fabrication 2 step: Chips can be replaced by users →　Field Stackable Key Technique: Inductive Coupling Through-Chip Interface（TCI)

CPU Core 35 bit Packet Structure 35 33 32 Header Payload 1 Network Interface Clock Link Rx Accelerator Core Blk Command/Address Single Packet Data Burst Multi-Packet Data Tx Data Link Rx Transfer Type: Tx Host Router Network Interfac e Packet En/Decode Blk Tx Rx Tx Blk Rx Tx Uplink 3 D Interconnect TCI Tx Rx Blk Tx Blk Rx TCI Network Interface Packet En/Decode Tx Rx Accelerator 2 Downlink 　　 Block diagram of scalable 3 D No. C using inductive-coupling Thru. Chip Interface (TCI). 　　8 Gbps 10 m. W/link 10^-9 error rate

Network IF MIPS CPU Core TEG TCI Tx TCI Rx Host CPU Chip Network IF 8 x 8 PE Array m-Controller Host C TCI Rx Tx Tx Rx Accelerator Chip Microphotograph of stacked test chips. Accelerato Host CPU + Accelerator x 3 Chip Stack Fabricated in 65 nm CMOS