Tbbmagossokmagos processzorok2 Sima Dezs 2014 Oktber Version 1

Többmagos/sokmagos processzorok-2 Sima Dezső 2014 Október Version 1. 4

Áttekintés • 1. Többmagos processzorok megjelenésének szükségszerűsége • 2. Homogén többmagos processzorok • • 2. 1 Hagyományos többmagos processzorok • 2. 2 Sokmagos processzorok 3. Heterogén többmagos processzorok • 3. 1 Mester/szolga elvű többmagos processzorok • 3. 2 Csatolt többmagos processzorok • 4. Kitekintés

3. Heterogén többmagos processzorok

3. Heterogén többmagos processzorok (1) Multicore processors Heterogenous multicores Homogenous multicores Conventional MC processors 2≤ Desktops n≤ 8 cores Manycore processors Master/slave architectures Add-on architectures with >8 cores Servers MPC CPU General purpose computing Experimental systems, prototypes/in production MM/3 D/HPC production stage 3. 1 ábra Többmagos processzorok főbb osztályai GPU HPC, mobiles production stage

3. 1 Heterogén többmagos mester/szolga elvű TP-ok A Cell processzor

3. 1 Heterogén mester/szolga elvű TP-ok - A Cell (1) Cell BE • Sony, IBM és Toshiba közös terméke • Cél: Játékok/multimédia, HPC alkalmazások Playstation 3 (PS 3) • Előzmények: 2000 nyara: 02/2006: 08/ 2007 05/ 2008 QS 2 x Blade Szerver család (2 Cell BE/blade) Az architektúra alapjainak meghatározása Cell Blade QS 20 Cell Blade QS 21 Cell Blade QS 22

3. 1 Heterogén mester/szolga elvű TP-ok - A Cell (2) SPE: Synergistic Procesing Element SPU: Synergistic Processor Unit SXU: Synergistic Execution Unit LS: Local Store of 256 KB SMF: Synergistic Mem. Flow Unit EIB: Element Interface Bus PPE: Power Processing Element PPU: Power Processing Unit PXU: POWER Execution Unit MIC: Memory Interface Contr. BIC: Bus Interface Contr. XDR: Rambus DRAM 3. 1. 1 ábra: A Cell BE blokk diagramja [1]

3. 1 Heterogén mester/szolga elvű TP-ok - A Cell (3) 3. 1. 2 ábra: A Cell BE lapka (221 mm 2, 234 mtrs) [1]

3. 1 Heterogén mester/szolga elvű TP-ok - A Cell (4) 3. 1. 3 ábra: A Cell BE lapka – EIB [1]

3. 1 Heterogén mester/szolga elvű TP-ok - A Cell (5) 3. 1. 4 ábra: Az EIB működési elve [1]

3. 1 Heterogén mester/szolga elvű TP-ok - A Cell (6) 3. 1. 5 ábra: Konkurens átvitelek az EIB-en [1]

3. 1 Heterogén mester/szolga elvű TP-ok - A Cell (7) Példa egy komplex alkalmazás futtatása (digitális TV dekódolása) a Cell processzoron [2

3. 1 Heterogén mester/szolga elvű TP-ok - A Cell (8) A Cell teljesítménye és a NIK részvétele a Cell teljesítmény-vizsgálataiban • Teljesítmény @ 3. 2 GHz: QS 21 Csúcs SP FP: 409, 6 GFlops (3. 2 GHz x 2 x 8 SPE x 2 x 4 SP FP/cycle) • Cell BE - NIK 2007: Faculty Award (Cell 3Đ app. /Teaching) 2008: IBM – NIK Kutatási Együttműködési Szerződés: Teljesítményvizsgálatok • IBM Böblingen Lab • IBM Austin Lab

3. 1 Heterogén mester/szolga elvű TP-ok - A Cell (9) The Roadrunner 6/2008 : International Supercomputing Conference, Dresden A világ 500 leggyorsabb számítógépe listáján (Top 500): 1. Roadrunner 1 Petaflops (1015) fenntartott teljesítmény (Linpack)

3. 1 Heterogén mester/szolga elvű TP-ok - A Cell (10) 3. 1. 6 ábra: A világ leggyorsabb számítógépe: IBM Roadrunner (Los Alamos 2008) [3]

3. 1 Heterogén mester/szolga elvű TP-ok - A Cell (11) 3. 1. 7 ábra: A Roadrunner főbb jellemzői [1]

3. 2 Heterogén csatolt többmagos processzorok

3. 2 Heterogén csatolt többmagos processzorok (1) Multicore processors Heterogenous multicores Homogenous multicores Conventional MC processors 2≤ Desktops n≤ 8 cores Manycore processors Master/slave architectures Add-on architectures with >8 cores Servers MPC CPU General purpose computing Experimental systems, prototypes/in production MM/3 D/HPC production stage 3. 2. 1 ábra: Többmagos processzorok főbb jellemzői GPU HPC, mpbiles production stage

3. 2 Heterogén csatolt többmagos processzorok (2) Csatolt elvű végrehajtás elve GPGPU-k esetén (a legegyszerűbb (kötegelt) szervezést feltételezve) [4] Host kernel 0<<<>>>() (Adatpárh. progr. ) kernel 1<<<>>>() Device

3. 2 Heterogén csatolt többmagos processzorok (3) Megjegyzés a működési elvhez • Heterogén csatolt többmagos processzorok: feldolgozás gyorsítók (accelerators) • A működési elv szempontjából előzmény: heterogén csatolt társprocesszoros rendszerek Példák: korai személyi számítógépek lebegőpontos társprocesszorokkal Intel 286 + 287 386 + 387 Az Intel 486 -nak már volt saját “on-chip” lebegőpontos egysége (FPU) (az SX és SL modelek kivételével)

3. 2 Heterogén csatolt többmagos processzorok (4) Heterogén csatolt többmagos processzorok legfontosabb implementációi Heterogén csatolt többmagos processzorok Integrált grafika Okostelefonok/táblagépek

3. 2. 1 Az Integrált grafika megjelenése

3. 2. 1 Az Integrált grafika megjelenése (1) Áttérés angol nyelvű slide-ok használatára

3. 2. 1 Az Integrált grafika megjelenése (2) Implementation of integrated graphics In the north bridge In a multi-chip processor package on a separate die On the processor die Both the CPU and the GPU are on separate dies and are mounted into a single package P IG GPU NB South Bridge Implementations about 1999 - 2009 Mem. CPU NB P P Mem. GPU CPU Mem. Periph. Contr. South Bridge Intel’s Havendale (DT) and Auburndale (M) (scheduled for 1 H/2009 but cancelled) Arrandale (DT, 1/2010) and Clarkdale (M, 1/2010) Intel’s Sandy Bridge (1/2011) and Ivy Bridge (4/2012) etc. AMD’s Swift (scheduled for 2009 but canceled) AMD’s Bobcat-based APUs (M, 1/2011) Llano APUs (DT, 6/2011) Trinity APUs (DT, Q 4/2012) etc.

3. 2. 1 Az Integrált grafika megjelenése (3) Implementation of integrated graphics In the north bridge In a multi-chip processor package on a separate die On the processor die Both the CPU and the GPU are on separate dies and are mounted into a single package P IG GPU NB South Bridge Implementations about 1999 - 2009 Mem. CPU NB P P Mem. GPU CPU Mem. Periph. Contr. South Bridge Intel’s 2. gen. Nehalem based Havendale (DT) and Auburndale (M) (scheduled for 1 H/2009 but cancelled) Westmere based Arrandale (DT, 1/2010) and Clarkdale (M, 1/2010) Intel’s Sandy Bridge (1/2011), Ivy Bridge (4/2012) etc. AMD’s Swift (scheduled for 2009 but canceled) AMD’s Bobcat-based APUs (M, 1/2011) Llano APUs (DT, 6/2011) Trinity APUs (DT, Q 4/2012) etc.

3. 2. 1 Az Integrált grafika megjelenése (4) Example 1: Intel’s Havendale (DT) and Auburndale (M) multi-chip CPU/GPU processor plans [5] • Revealed in 9/2007. • Scheduled for 1 H/2009 but cancelled about 1/2009. • Both parts were based on the 2. gen. Nehalem (Lynnfield) architecture (45 nm), as shown below. Core PCI-E Thread Power Core DDR 3 IMC Graphics Same LGA 1160 platform Thread 8 M Thread PCI-E 4 M Graphics GPU DDR 3 IMC DDR 3 MCP Processor Display Digital Thread Power Thread DMI Analog Core Havendale processor (Multi-chip package – MCP) Lynnfield processor (Monolithic die) Schedule: • 2 H ’ 08 First Samples • 1 H ’ 09 Production • TDP < 95 W I/O Control Processors I/O functions Ibexpeak PCH VGA PCIe, SATA, NVRAM, etc. SDVO, HDMI Display Port, DVI Display Link DMI (Direct Media Interface) 4 PCIe lanes) Display Analog Digital I/O Control Processors I/O functions Ibexpeak PCH No integrated graphics PCIe, SATA, NVRAM, etc.

3. 2. 1 Az Integrált grafika megjelenése (5) Example 2: Intel’s Westmere-EP based multi-chip CPU/GPU processors (2010)-1 [6] Clarkdale (desktop) Arrandale (mobile) The CPU and the GMA chips are connected by the QPI bus.

3. 2. 1 Az Integrált grafika megjelenése (6) Positioning of Clarkdale (DT) and Arrandale (M) in Intel’s roadmap [7]

3. 2. 1 Az Integrált grafika megjelenése (7) Single chip “chipset”, called PCH for Intel’s Westmere-EP based multi-chip CPU/GPU processors (2010) [7] PCH (Peripheral Control Hub)

(Dedicated graphics 3. 2. 1 Az Integrált grafika megjelenése (8 a) via graphics card) Removing the memory controller (MC) from the north bridge to the processor (IMC) [7] (Dedicated graphics via graphics card)

(Dedicatedmegjelenése graphics 3. 2. 1 Az Integrált grafika (8) via graphics card) Removing integrated graphics (IGFX) from the north bridge to the processor [7] (Dedicated graphics via graphics card) On extra die

(Dedicated graphics 3. 2. 1 Az Integrált grafika megjelenése (8 b) via graphics card) Connecting discrete graphics immediately to the processor instead the north bridge [7] (Dedicated graphics via graphics card) PCIe 2. 0

3. 2. 1 Az Integrált grafika megjelenése (9) Implementation of commercial graphics on the processor die Implementation of integrated graphics In the north bridge In a multi-chip processor package on a separate die On the processor die Both the CPU and the GPU are on separate dies and are mounted into a single package P IG GPU NB Mem. South Bridge Implementations around 1999 - 2009 CPU NB P P Mem. GPU CPU Mem. Periph. Contr. South Bridge Intel’s Havendale (DT) and Auburndale (M) (scheduled for 1 H/2009 but cancelled) Arrandale (DT, 1/2010) and Clarkdale (M, 1/2010) Intel’s Sandy Bridge (1/2011) and Ivy Bridge (4/2012) etc. AMD’s Swift (scheduled for 2009) AMD’s Bobcat-based APUs (M, 1/2011) and Llano APUs (DT, 6/2011) Trinity APUs (DT, Q 4/2012) etc.

3. 2. 2 Intel’s Sandy Bridge

3. 2. 2 Intel’s Sandy Bridge (1) 3. 2. 2 Intel’s Sandy Bridge [8] Key microarchitecture features of the Sandy Bridge vs the Nehalem

3. 2. 2 Intel’s Sandy Bridge (2) Die plot of the 4 C Sandy Bridge processor [9] 256 KB L 2 (9 clk) Hyperthreading 32 K L 1 D (3 clk) AES Instr. AVX 256 bit VMX Unrestrict. 4 Operands 20 nm 2 / Core @ 1. 0 1. 4 GHz (to L 3 connected) (25 clk) 256 b/cycle Ring Architecture DDR 3 -1600 Sandy Bridge 4 C 32 nm 995 mtrs/216 mm 2 ¼ MB L 2/C 8 MB L 3 PCIe 2. 0

3. 2. 2 Intel’s Sandy Bridge (3) Block diagram of Intel’s Sandy Bridge with 6 Series PCH [10] Core i 3 -21 xx, 2 C, 2/2011 Core i 5 -23 xx/24 xx/25 xx, 4 C, 1/2011 Core i 7 -26 xx, 4 C, 1/2011 1 Intel 6 series PCH 1 1 Except P 67 that does not provide a display controller in the PCH

3. 2. 2 Intel’s Sandy Bridge (4) Graphics performance increase of subsequent Core generations [33] Haswell Ivy Bridge Sandy Bridge

3. 2. 3 AMD’s Swift Fusion APU plan

3. 2. 3 AMD’s Swift Fusion APU plan (1) 3. 2. 3 AMD’s Swift Fusion APU plan Preliminaries In 10/2006 AMD acquired the graphics firm ATI and at the same day they announced that “AMD plans to create a new class of x 86 processors that integrate the central processing unit (CPU) and graphics processing unit (GPU) at the silicon level, codenamed “Fusion [13]. ” Remark Although in the above statement AMD designated the silicon level integration of the CPU and GPU as the Fusion initiative, in some other publications they call both the package level and the silicon level integration of the CPU and GPU as the Fusion technology, as shown in the next figure [14]

3. 2. 3 AMD’s Swift Fusion APU plan (2) Extended interpretation of the term Fusion technology in some AMD publications [14] Despite this disambiguation, subsequently AMD understood the term Fusion usually as the silicon level integration of the CPU and the GPU.

3. 2. 3 AMD’s Swift Fusion APU plan (3) • In 12/2007 at their Financial Analyst Day AMD gave birth to a new term by designating their processors implementing the Fusion concept as APUs (Accelerated Processing Units). • At the same time AMD announced their first APU family called the Swift family [15] as well.

3. 2. 3 AMD’s Swift Fusion APU plan (4) • In 11/2008 again at their Financial Analyst Day AMD postponed the introduction of Fusion-based APU processors until the company transitions to the 32 nm technology [16] [17]. No Swift APU!

3. 2. 3 AMD’s Swift Fusion APU plan (5) Remark This is a similar move as done by Intel with their 45 nm Havendale (DT) and Auburndale (M) in-package integrated multi-chip CPU+GPU projects. As leaked from industry sources in 1/2009 Intel canceled their 45 nm multi-chip processor plans in favor of 32 -nm multi-chip processors to be introduced in Q 1/2010 [18].

3. 2. 4 AMD’s K 12 (Llano)-based APU lines

3. 2. 4 AMD’s K 12 (Llano)-based APU lines-1 Fam. 15 h Mod. 10 h-1 Fh Fam. 15 h Mod. 00 h-0 Fh 15 h s K 10 ily n e Fam. 15 h Mod. 30 h-3 Fh Steamroller lin es 3. 2. 4 Overview of AMD’s desktop and mobile APU lines-1 (based on [37]) lin es Fam. 12 h Hound (K 10. 5/Stars) n) io us Bobcat Fam. 14 h U (F Brazos (Zacate) 1 -2 Cores 1 MB DX 11 GPU Core DDR 3 Jaguar Fam. 16 h 16 – Hound (K 10. 5/Stars) ily Family 11 h 12 h K 10 h A P / K 10. 5 / F a m i l G P y U -l 11 h es s l i Fa m 28 nm Table t Brazos (Desna) 2 Cores 1 MB DX 11 GPU Core DDR 3 Fa m Fam. 14 h Jaguar Fam. 16 h

3. 2. 4 AMD’s K 12 (Llano)-based APU lines-2 3. 2. 4 Overview of AMD’s notebook and tablet APU lines-2 PWc Basically PWc tuned by Tdie m PWc ≤ TDP: Turbo mode PWc < TDP: Decrease fc PWc ≤ TDP: Turbo mode PWc ≥ TDP: Decrease fc Tdie c ≤ Tdie c max: Turbo mode Tdie c > Tdie c max: Decrease fc If Tdie m < Tdie m max increase fc additionally up to fc max , as long as Tdie m < Tdie m max If Tdie m < Tdie m max increase fc additionally up to fc max , as long as Tdie m ≤ Tdie m max Intel’s Turbo Boost in Nehalem (2008) Westmere based Arrandale M (2010) Basically Tdie c tuned by Tdie m Tdie c Intel’s Turbo Boost 2. 0 in Sandy Bridge (2011) Ivy Bridge (2012) Haswell (2013) AMD’s Turbo Core 2. 0 in K 12 Llano APU (2011) K 16 Jaguar based Kabini/Temash (2013) PWc: Calculated power consumption PWm: Measured power consumption AMD’s Turbo Core 3. 0 in K 15 Piledriver based Trinity (2012) AMD’s Hybrid Boost in K 15 Piledriver based Richland (2013) Tdie c: Calculated die temperature Tdie m: Measured die temperature http: //www. anandtech. com/show/7974/amd-beema-mullins-architecture-a 10 -micro-6700 t-performance-preview

3. 2. 5 AMD’s K 12 (Llano)-based APU lines (3) 3. 2. 4 AMD’s Llano-based APU lines [19] • Introduced: 6/2011. • The Llano line belongs to the Fusion APU (Accelerated Processing Unit) series as it includes beyond a number of CPUs also a GPU to accelerate vision computing (graphics and media). • Processors of the Llano lines have up to 4 CPU cores and a GPU. Nevertheless, AMD sells Llano based desktop lines as well with disabled GPUs. These lines are branded as Athlon II X 4/X 2 or Sempron lines. • 32 nm technology, 228 mm 2, 1450 mtrs.

3. 2. 5 AMD’s K 12 (Llano)-based APU lines (4) Die plot of the Llano processor [20]

3. 2. 5 AMD’s K 12 (Llano)-based APU lines (5) Example: AMD’s Llano-based A-series mobile lines [21]

3. 2. 5 AMD’s K 12 (Llano)-based APU lines (6) Conceptual difference between AMD’s Fusion APU’s and Intel’s Sandy Bridge CPUs [22]

3. 2. 5 AMD’s K 12 (Llano)-based APU lines (7) AMD’s Llano APU processor with the A 75 FCH [23] Lynx platform FCH: Fusion Control Hub

3. 2. 5 AMD’s K 12 (Llano)-based APU lines (8) Internal buses introduced in Llano’s Integrated Northbridge-1 [20]

3. 2. 5 AMD’s K 12 (Llano)-based APU lines (9) Internal buses introduced in Llano’s Integrated Northbridge-2 [20]

3. 2. 5 Okostelefonok, táblagépek

3. 2. 5 Okostelefonok, táblagépek-1 Ld. később külön fejezetként.

3. 2. 5 Okostelefonok, táblagépek-2 3. 2. 5 Okostelefonok/táblagépek Példa 1: Texas OMAP 4 (OMAP 4460) Source: TI’s OMAP 4460 in Samsung GALAXY Nexus with Android 4. 0 October 21, 2011

3. 2. 5 Okostelefonok, táblagépek-3 Példa 2: Texas OMAP 5 (OMAP 5430) A 15 MPCore: Up to 4 cores, in Texas’s implementation: 2 cores

3. 3. 2 Okostelefonok/táblagépek (4)

3. 3. 2 Okostelefonok/táblagépek (5) Megjegyzés 9/2012 Texas bejelentés: az OMAP család fejlesztésének leállítása, fókuszálás autóipari elektrónika További gyártók: Qualcomm, Samsung, NVIDIA, Intel

4. Kitekintés

4. Kitekintés (1) Kitekintés Heterogenous multicores Master/slave architectures Add-on architectures Több CPU Több gyorsító 4. 1 ábra: Hetererogén többmagos processzorok várható fejlődése

Referenciák

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Köszönöm a figyelmet!

3. 2. 6 AMD’s Piledriver-based Trinity desktop APU line (6) Trinity’s Unified North Bridge [] http: //www. hardwarecanucks. com/forum/hardware-canucks-reviews/54260 -amd-trinity-going-m

GNB: Graphics North Bridge RMB: Radeon Memory Bus http: //hothardware. com/Reviews/AMD-Trinity-A 104600 M-Processor-Review/? page=3

Trinity Unified North Bridge http: //www. hardwarecanucks. com/forum/hardware-canucks-reviews/54260 -amd-trinity-going-mobile-new-apu-4. html

http: //www. hardwarecanucks. com/forum/hardware-canucks-reviews/54260 -amd-trinity-going-mobile-new-apu-4. html

The links between each section of the APU follow in the same footsteps as the previous generation but AMD has refined certain interconnects with the goal of speeding up information transfers. The AMD Fusion Compute Link is still considered to be a medium bandwidth connection which manages the complex interaction between the onboard GPU, the CPU’s cache and the system memory. Unlike in the past, AMD has finally refined this interconnect, giving the GPU direct access to a coherent memory space while the CPU can now directly access the GPU’s dedicated framebuffer if needed. This is one of the primary reasons why Trinity’s theoretical data throughput has jumped from 572 GFLOPS to 736 GFLOPS. The Radeon Memory Bus on the other hand is the all-important link between the onboard graphics coprocessor and the primary on-chip memory controller. Rather than acting like a traffic cop (a la Fusion Compute Link) which tries to direct the flow of information, this memory bus is all about the GPU having unhindered high bandwidth access to the system’s memory controllers. In the previous generations of AMD IGPs, before Llano came around, the Northbridge’s graphics processor had to jump through a series of hoops before gaining access to onboard memory which is partially why 128 MB of “Side. Port” memory was sometimes added. However, the APU’s single chip, all in one solution allows for the elimination of many potential bottlenecks. http: //www. hardwarecanucks. com/forum/hardware-canucks-reviews/54260 -amd-trinity-going-mobile-new-apu-4. html

Trinity This unit adds virtual address access discrete graphics, allowing an external GPU to directly access the same virtual address space as the CPU through page tables. As you can imagine, this is a key part of the programming model for AMD’s Heterogeneous Systems Architecture (HSA). http: //www. tomshardware. com/reviews/a 10 -4600 m-trinity-piledriver, 3202 -4. html