Tbbmagos Processzorok 5 Sima Dezs 2007 szi flv
Többmagos Processzorok (5) Sima Dezső 2007 őszi félév (Ver. 2. 1) Dezső Sima, 2007
10. 3 IBM’s MC processors • 10. 3. 1 POWER line • 10. 3. 2 Cell BE
10. 3 IBM’s MC processors 10. 3. 1 POWER line • POWER 4+ • POWER 5+ • POWER 6 10/2001 11/2002 180 nm 130 nm 5/2004 130 nm 10/2005 90 nm 65 nm 2007
10. 3. 1 Evolution of IBM’s major RISC lines Figure: The evolution of IBM’s major RISC lines
10. 3. 1 POWER 4 (1) Service Processor Core interface Unit (crossbar) Power On Reset Built-In-Self. Test Non-Cacheable Unit Multi. Chip Module Figure : POWER 4 chip logical view [3. 6]
10. 3. 1 POWER 4 (2) Figure: Logical view of the L 3 controller [3. 5]
10. 3. 1 POWER 4 (3) Figure: The memory cotroller of the POWER 4 [3. 5]
10. 3. 1 POWER 4 (4) Fabric Controller Figure: I/O controller of the POWER 4 [3. 5]
10. 3. 1 POWER 4 (5) Figure: POWER 4 chip [3. 11]
10. 3. 1 POWER 4 (6) POWER line POWER 4 Dual/Quad-Core DC Introduced 10/2001 Technology 180 nm Die size 412 mm 2 Nr. of transistors 174 mtrs fc L 2 L 3 [GHz] 1. 3 Size/allocation 1. 44 MB/shared Implementation On-chip Size 32 MB Implementation Tags on-chip, data off-chip Mem. contr. Off-chip TDP 115/125 [W] Packaging SCM 1/MCM 2 Dual threaded Power management 1 2 3 L 3 impl. Tags on-chip L 3 size 32 MB SMC: Single Chip Module MCM: Multi Chip Module DCM: Dual Chip Module 4 5 6 DCM: Dual Core Module QCM: Quad Core Module DPM: Dynamic Power Management Table: Main features of IBM’s dual-core POWER line
10. 3. 2 POWER 4+ (1) Figure: New features of the POWER 5+ [3. 3]
10. 3. 1 POWER 4+ (2) POWER line POWER 4+ DC DC Introduced 10/2001 11/2002 Technology 180 nm 130 nm Die size 412 mm 2 380 mm 2 Nr. of transistors 174 mtrs 184 mtrs 1. 3 1. 7 Size/allocation 1. 44 MB/shared 1. 5 MB/shared Implementation On-chip 32 MB Dual/Quad-Core fc L 2 L 3 [GHz] Size Implementation Tags on-chip, data off-chip Mem. contr. Off-chip On-chip TDP 115/125 70 SCM 1/MCM 2 [W] Packaging Dual threaded Power management L 3 impl. Tags on-chip L 3 size 32 MB 1 2 3 SMC: Single Chip Module MCM: Multi Chip Module DCM: Dual Chip Module 4 5 6 DCM: Dual Core Module QCM: Quad Core Module DPM: Dynamic Power Management Table: Main features of IBM’s dual-core POWER line
10. 3. 1 POWER 5 (1) Figure 5. 14: Contrasting POWER 4 and POWER 5 system structures [3. 1]
10. 3. 1 POWER 5 (2) Figure: Block diagram of the POWER 5 (1) [3. 1]
10. 3. 1 POWER 5 (3) Figure: Block diagram of the POWER 5 (2) [3. 12]
10. 3. 1 POWER 5 (4) Figure: Floorplan of the POWER 5 [3. 13]
10. 3. 1 POWER 5 (6) POWER 4 180 nm, 412 mm 2 POWER 5 130 nm, 389 mm 2 (~3 % enlarged) Figure: Contrasting the floor plans of the POWER 4 and POWER 5 dies [3. 11], [3. 13]
10. 3. 1 POWER 5 (7) POWER 5+ Dual-Core Module Figure: Packaging alternatives of the POWER 4/5 processors Source: Partridge R. and Ghatpande S. , IBM Introduces POWER 5+ and Quad-Core Modules in System p 5, ” Tech Trends Monthly, Nov. /Dec. 2005,
10. 3. 1 POWER 5 (8) POWER 4 MCM Photo 32 -way System Showing 4 MCMs and L 3 Cache Figure: Quad–Chip POWER 4 module (MCM) and a 32 -way POWER 4 system [3. 7]
10. 3. 1 POWER 5 (9) Figure. : Interpretation of Dual-Chip Modules (DCMs) and Multi-Chip Modules (MCM) of the POWER 5 [3. 7]
10. 3. 1 POWER 5 (10) Figure: Photos of Dual-Chip Modules (DCMs) and Multi-Chip Modules (MCM) of the POWER 5 [3. 7]
10. 3. 1 POWER 5 (11) Figure: The Multi-chip module of the POWER 5 [3. 10]
10. 3. 1 POWER 5 (12) POWER line POWER 4+ POWER 5 DC DC DC Introduced 10/2001 11/2002 5/2004 Technology 180 nm 130 nm Die size 412 mm 2 380 mm 2 389 mm 2 Nr. of transistors 174 mtrs 184 mtrs 276 mtrs 1. 3 1. 7 1. 65/1. 9 Size/allocation 1. 44 MB/shared 1. 5 MB/shared 1. 9 MB/shared Implementation On-chip 32 MB 36 MB Dual/Quad-Core fc L 2 L 3 [GHz] Size Implementation Tags on-chip, data off-chip Mem. contr. Off-chip On-chip TDP 115/125 70 80 (est) SCM 1/MCM 2 DCM 3/MCM 2 [W] Packaging Dual threaded Power management DPM 6 L 3 impl. Tags on-chip L 3 size 32 MB 36 MB 1 2 3 SMC: Single Chip Module MCM: Multi Chip Module DCM: Dual Chip Module 4 5 6 DCM: Dual Core Module QCM: Quad Core Module DPM: Dynamic Power Management Table: Main features of IBM’s dual-core POWER line
10. 3. 1 POWER 5+ (1) Figure: Block diagram of the POWER 5+ Source: Vetter S. et al. , IBM System p 5 Quad-Core Module Based on POWER 5+ Technology, ” Redbooks paper, IBM Corp. 2006, http: //www. redbooks. ibm. com/redpapers/pdfs/redp 4150. pdf
10. 3. 1 POWER 5+ (2) Figure: Dual-Core Modules (DCMs) and Quad-Core Modules (QCM) of the POWER 5+ [3. 14]
10. 3. 1 POWER 5+ (3) POWER line POWER 4+ POWER 5+ DC DC Introduced 10/2001 11/2002 5/2004 10/2005 Technology 180 nm 130 nm 90 nm Die size 412 mm 2 380 mm 2 389 mm 2 230 mm 2 Nr. of transistors 174 mtrs 184 mtrs 276 mtrs 1. 3 1. 7 1. 65/1. 92 Size/allocation 1. 44 MB/shared 1. 5 MB/shared 1. 9 MB/shared Implementation On-chip 36 MB Dual/Quad-Core fc L 2 L 3 [GHz] Size 32 MB 10. 3 Implementation Tags on-chip, data off-chip Mem. contr. Off-chip On-chip TDP 115/125 70 80 (est) 70 SCM 1/MCM 2 DCM 3/MCM 2 DCM 4/QCM 5 DPM 6 [W] Packaging Dual threaded Power management L 3 impl. Tags on-chip L 3 size 32 MB 36 MB 1 2 3 SMC: Single Chip Module MCM: Multi Chip Module DCM: Dual Chip Module 4 5 6 DCM: Dual Core Module QCM: Quad Core Module DPM: Dynamic Power Management Table: Main features of IBM’s dual-core POWER line
10. 3. 1 POWER 6 (1) POWER 6 POWER 5+ Hardware support of decimal arithmetic Figure: Contrasting the block diagrams of the POWER 5 and POWER 6 processors [3. 15]
10. 3. 1 POWER 6 (2) POWER line POWER 4+ POWER 5+ POWER 6 DC DC DC Introduced 10/2001 11/2002 5/2004 10/2005 2007 Technology 180 nm 130 nm 90 nm 65 nm Die size 412 mm 2 380 mm 2 389 mm 2 230 mm 2 341 mm 2 Nr. of transistors 174 mtrs 184 mtrs 276 mtrs 750 mtrs 1. 3 1. 7 1. 65/1. 92 4 -5 Size/allocation 1. 44 MB/shared 1. 5 MB/shared 1. 9 MB/shared 2*4 MB/private Implementation On-chip On-chip 32 MB 36 MB 64 MB? Dual/Quad-Core fc L 2 L 3 [GHz] Size Implementation Tags on-chip, data off-chip Mem. contr. Off-chip On-chip TDP 115/125 70 80 (est) 70 ~100 SCM 1/MCM 2 DCM 3/MCM 2 DCM 4/QCM 5 n. a. DPM 6 n. a. [W] Packaging Dual threaded Power management L 3 impl. Tags on-chip L 3 size 32 MB 36 MB 32 MB 1 2 3 SMC: Single Chip Module MCM: Multi Chip Module DCM: Dual Chip Module 4 5 6 DCM: Dual Core Module QCM: Quad Core Module DPM: Dynamic Power Management Table: Main features of IBM’s dual-core POWER line
10. 3 IBM’s MC processors 10. 3. 2 Cell BE • Cell BE 2/2006 90 nm
10. 3. 2 Cell BE (1) Figure: The history and development cost of the Cell BE [3. 17], [3. 22]
10. 3. 2 Cell BE (2) AUC: Atomic Update Cache BIC: Bus Interface Contr. EIB: Element Interface Bus LS: Local Store of 256 KB MFC: Memory Flow Controller MIC: Memory Interface Contr. PPE: Power Processing Element PXU: POWER Execution Unit SMF: Synergistic Memory Flow Unit SPU: Synergistic Processor Unit SXU: Synergistic Execution Unit XDR: Rambus DRAM Figure: Block diagram of the Cell BE [3. 19]
10. 3. 2 Cell BE (3) Design parameters of the Cell BE: PPE: dual-threaded > 200 GFLOPS (SP) > 20 GFLOPS (DP) > 25 GB/s memory BW > 75 GB/s I/O BW > 300 GB/s EIB BW fc > 4 GHz (lab) Figure: Main design parameters of the Cell BE [3. 28]
10. 3. 2 Cell BE (4) Figure : Cell SPE architecture [3. 16]
10. 3. 2 Cell BE (5) Figure: Block diagram of the SPE [3. 19]
10. 3. 2 Cell BE (6) Figure: Pipeline stages of the Cell BE [3. 19]
10. 3. 2 Cell BE (7) Figure: Floor plan of a single SPE [3. 19]
10. 3. 2 Cell BE (8) Principle of operation of the Element Interface Bus (EIB) [3. 23]
10. 3. 2 Cell BE (9) Figure: The Element Interface Bus EIB) [3. 19]
10. 3. 2 Cell BE (10) Figure: The Synergistic Memory Flow unit (SMF) [3. 19]
Figure: PPE block diagram [3. 28]
10. 3. 2 Cell BE (11) 235 mm 2 241 mtrs Figure: Floor plan of the Cell BE processor [3. 19]
10. 3. 2 Cell BE (12) Series Cell BE Implementation Heterogeneous 1 x. PPE, 8*SPE Architecture Power. PC 2. 02 PPE: 64 -bit RISC SPE: Dual-issue 32 -bit SIMD with 128 bit capability Cores Introduction 9/2006 (in the QS 20 Blade. Center) Technology 90 nm Die size 221 mm 2 Nr. of transistors 234 mtrs fc [GHz] 3. 0/3. 2 PPE: 512 KB SPE: 256 KB Local Store (128*128 bit) L 2 L 3 Memory controller Interconnection network Memory bandwidth On-chip Ring based 25 GB/s I/O bandwidth Up to 75 MB/s TDP 95 W @ 3 GHz [W] Multithreading PPE: 2 -way SPE: Table: Main features of the IBM’s Cell BE
10. 3. 2 Cell BE (13) Figure: Cell BE Blade Roadmap Source: Brochard L. , A Cell History, ” Cell Workshop, April, 2006 http: //www. irisa. fr/orap/Constructeurs/Cell%20 Short%20 Intro%20 Luigi. pdf
10. 3. 2 Cell BE (14) Figure: Roadmap of the Cell BE Source: Hofstee H. P. , „Real-time Superconputing and Technology for Games and Entertainment, ” 2006, http: //www. cercs. gatech. edu/docs/SC 06_Cell_111606. pdf
10. 3 Literature (1) POWER 4, POWER 4+ [3. 1] Barney B. , „IBM POWER Systems Overview”, Livermore Computing, 2006, http: //www. llnl. gov/computing/tutorials/ibm_sp/ [3. 2] De. Mone P. , „Sizing Up the Super Heavyweights, ” Real Word Technologies, Sept. 2004, http: //h 21007. www 2. hp. com/dspp/files/unprotected/Itanium/sizingsuperheavys. pdf [3. 3] Grassl C. , „New IBM Components for HPCx”, Dec. 2003, http: //www. hpcx. ac. uk/about/events/annual 2003/Grassl. pdf [3. 4] Krevell K. , „IBM’s POWER 4 Unveiling Continuues”, Microprocessor Report, Nov. 2000, pp- 1 -4 [3. 5] Tendler, J. M. , Dodson, S. , Fields S. , Le H. , Sinharoy B. : Power 4 System Microarchitecture, IBM Server, Technical White Paper, October 2001, http: //www-03. ibm. coom/servers/eserver/pseries/hardware/whitepapers/power 4. pdf [3. 6] Tendler, J. M. , Dodson, S. , Fields S. , Le H. , Sinharoy B. : Power 4 System Microarchitecture, , IBM J. Res. & Dev. Vol. 46, No. 1, Jan. 2002, pp. 5 -25, http: //www. research. ibm. com/journal/rd/461/tendler. pdf POWER 5, POWER 5+ [3. 7] Barney B. , „IBM POWER Systems Overview”, Livermore Computing, 2006, http: //www. llnl. gov/computing/tutorials/ibm_sp/ [3. 8] De. Mone P. , „Sizing Up the Super Heavyweights, ” Real Word Technologies, Sept. 2004, http: //h 21007. www 2. hp. com/dspp/files/unprotected/Itanium/sizingsuperheavys. pdf [3. 9] Grassl C. , „New IBM Components for HPCx”, Dec. 2003, http: //www. hpcx. ac. uk/about/events/annual 2003/Grassl. pdf [3. 10] Kalla R. , „IBM’s POWER 5 Microprocessor Design and Methodology, ” 2003, www-csl. csres. utexas. edu/users/billmark/teach/cs 352 -05 -spring/lectures/Lecture 22 -Ron. Kalla. IBM. pdf
10. 3 Literature (2) POWER 5, POWER 5+ (cont. ) [3. 11] Kalla R. , Sinharoy B. , Tendler J. : Simultaneous Multi-threading Implementation in Power 5 – IBM’s Next Generation POWER Microprocessor, 2003 http: //www. hotchips. org/archives/hc 15/3_Tue/11. ibm. pdf [3. 12] Krevell K. , „POWER 5 Tops on Bandwidth”, Microprocessor Report, Dec. 2003 http: //studies. ac. upc. edu/ETSETB/SEGPAR/microprocessors/power 5%20(2)%20(mpr). pdf [3. 13] Shinharoy B. , Kalla R. N. , Tendler J. M. , Eickenmeyer R. J. , Joyner J. B. , „POWER 5 system microarchitecture, ” IBM J. R&D, Vol. 49, No. 4/5, 2005, pp. 505 -521 [3. 14] Vetter S. et al. , IBM System p 5 Quad-Core Module Based on POWER 5+ Technology, ” Redbooks paper, IBM Corp. 2006, http: //www. redbooks. ibm. com/redpapers/pdfs/redp 4150. pdf POWER 6 [3. 15] Kanter D. , „IBM Previews the Power 6, ” Oct. 2006, dkanter@realwordtech. com Cell BE [3. 16] Blachford N. : „Cell Architecture Explained Version 2”, http: //www. blachford. info/computer/Cell 1_v 2. html [3. 17] Brochard L. , A Cell History, ” Cell Workshop, April, 2006 http: //www. irisa. fr/orap/Constructeurs/Cell%20 Short%20 Intro%20 Luigi. pdf [3. 18] Day M. and Hofstee P. , „Hardware and Software Architectures for the Cell Broadband Engine processor, ” CODES, Sept. 2006, http: //www. casesconference. org/cases 2005/pdf/Cell-tutorial. pdf [3. 19] Gshwind M. , „Chip Multiprocessing and the Cell BE, ” ACM Computing Frontiers, 2006, http: //beatys 1. mscd. edu/compfront//2006/cf 06 -gschwind. pdf
10. 3 Literature (3) Cell BE (cont. ) [3. 20] Gschwind M. , Hofstee H. P. , Flachs B. K. , Hophkins M. , Watanabe Y. , Yamazaki T „Synergistic Processing in Cell's Multicore Architecture, ” IEEE Micro, Vol. 26, No. 2, 2006, pp. 10 -24 [3. 21] Hofstee H. P. , „Real-time Superconputing and Technology for Games and Entertainment, ” 2006, http: //www. cercs. gatech. edu/docs/SC 06_Cell_111606. pdf [3. 22] Hofstee H. P. , „Cell today and tomorrow, ” 2005, http: //www. stanford. edu/class/ee 380/Abstracts/Cell_060222. pdf [3. 23] Keable C. , „And we also have hardware. . . ” 17 th Machine Evaluation Workshop, Dec. 2006, http: //www. cse. clrc. ac. uk/disco/mew 17/talks/Keable_IBM_MEW 17. pdf [3. 24] Krolak D. , „Unleashing the Cell Broadband Engine Processor, ” MPR Fall Proc. Forum, Nov. 2005, http: //www-128. ibm. com/developerworks/power/library/pa-fpfeib/? ca=dgr-lnxw. Cell. Connects [3. 25] Krewell K. , „Cell Moves Into The Limelight, ” Microprocessor Report, Febr. 14 2005, pp. 1 -9 [3. 26] Solie, D. , „Technology Trends Presentation, ” Power Symposium, Aug. 2006, http: //www-03. ibm. com/procurement/proweb. nsf/objectdocswebview/ file 14+-+darryl+solie+-+ibm+power+symposium+presentation/$file/ 14+-+darryl+solie-ibm-power+symposium+presentation+v 2. pdf [3. 27] - „Cell Broadband Engine processor – based systems, ” White Paper, IBM Corp. , 2006 [3. 28] - „Cell Architecture”, Course Code L 1 T 1 H 1 -10, 2006, http: //www. power. org/resources/devcorner/cellcorner/Cell. Training_Track 1/Course. Code_L 1 T 1 H 1 -10_ Cell. Architecture. pdf
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