Tbbmagos Processzorok 3 Sima Dezs 2007 szi flv

Többmagos Processzorok (3) Sima Dezső 2007 őszi félév (Ver. 2. 1) Dezső Sima, 2007

10. 1. 3 Dual/quad-core server processors Dual-Core Xeon UP-lines Dual/Quad-Core Xeon DP-lines Dual-Core Xeon MP-lines

10. 1. 3 Dual/quad-core server processors Dual-Core Xeon UP-lines • Xeon 3000 - line Core 2 Duo 9/2006 (Core based, monolithic, dual-core) 60 nm

Xeon 3000 UP-line (1)(Conroe) 10. 1. 3 Xeon Series Dual/Quad-Core Models 3000 (Conroe) DC 3040 -3070 Microarchitecture Cores E 6300 -E 6700 Intro. 9/2006 Technology 65 nm Die size 143 mm 2 Nr. of transistors 291 mtrs fc 1. 86 -2. 66 [GHz] L 2 2*4 MB FSB [MT/s] TDP [W] Socket 1066 65 FC-LGA 6 EM 64 T HT ED VT EIST La Grande AMT 2 Table: Main features of the dual-core Xeon 3000 UP-line [1. 8], [1. 9]

10. 1. 3 Dual/quad-core server processors Dual/Quad-Core Xeon DP-lines • Xeon DP 2. 8 Paxville DP 10/2005 90 nm (Netburst based, multi-chip, two Irwindale cores) • Xeon 5000 line Dempsey 5/2006 65 nm (Netburst based, multi-chip, two Cedar Mill cores) • Xeon 5100 line Woodcrest 6/2006 65 nm 11/2006 65 nm (Core based, monolithic, dual-core) • Xeon 5300 line Clovertown (Core based, multi-chip, two Woodcrest chips)

10. 1. 3 Xeon DP 2. 8 (Paxville DP) (1) Intel’s first 64 -bit Xeon Nocona Irwindale (L 2 enlarged to 2 MB) (DP enhanced Prescott) Nocona Paxville (2 x Irwindale cores) (DP enhanced Prescott 2 M) 6/2004 10/2004 2/2005 9/2005 10/2005 11/2005 90 nm 112 mm 2 125 mtrs 90 nm 135 mm 2 169 mtrs 90 nm 2 x 135 mm 2 2 x 169 mtrs Xeon DP 2. 8 – 3. 4 Xeon DP 2. 8 J - 3. 4 J Xeon DP 2. 8 – 3. 6 Xeon DP 3. 8 Xeon DP 2. 8 Xeon MP 7020 -7041 m. PGA 604 In contrast: corresponding desktop processors have the LGA 775 socket. m. PGA 604 Figure: Genealogy of the Xeon Paxville core Sources: http: //www. theinquirer. net/default. aspx? article=16879 http: //www. gamepc. com/labs/view_content. asp? id=x 36 o 252&page=2 http: //www. xbitlabs. com/articles/cpu/display/opteron-xeon-workstation_5. html

10. 1. 3 Xeon DP 2. 8 (Paxville DP) (2) Heat Sink Die size capacitors FC-m. PGA 4 package Pin side capacitors Package pin The FC-m. PGA package interfaces with the motherboard via an m. PGA 604 socket Figure: Packaging of the Paxville processor Source: - „Dual-Core Intel Xeon Processor 2. 80 GHz Datasheet, ” Oct. 2005, http: //download. intel. com/design/Xeon/datashts/30915801. pdf

10. 1. 3 Xeon DP 2. 8 (Paxville DP) (3) Figure Connecting the two Irwindale cores in the large Paxville Package (? ) [1. 3]

10. 1. 3 Xeon DP 2. 8 (Paxville DP) (4) Figure: Packaging of the Paxville (two Irwindale dies are mounted on a carrier and the carrier is packaged as a 604 package” Source: Conolly C. , „Intel Paxville Dual Core Xeon and the ASsus PVL-D Intel 7520, ” Oct. 2005, http: //www. gamepc. com/labs/view_content. asp? id=paxville&page=1

10. 1. 3 Xeon DP 2. 8 (Paxville DP) (5) Series Dual/Quad-Core Models (Paxville DP) DC Xeon DP 2. 8 Microarchitecture Netburst Cores 2*Irwindale dies Intro. 10/2005 Technology 90 nm Die size 2*135 mm 2 Nr. of transistors 2*169 mtrs fc [GHz] L 2 2. 8 2*2 MB FSB [MT/s] 800 TDP [W] 135 Socket PGA 604 EM 64 T HT ED VT EIST La Grande AMT 2 Table: Dual-Core Xeon DP-lines (1) [1. 8], [1. 9]

10. 1. 3 Xeon 5000 DP-line (Dempsey) (1) Figure: Block diagram of the Dempsey (Cedar Mill-based) Source: Inkley B. and Tetrick S. , „Intel Multi-core Architecture and implementations, ” IDF, March 2006, http: //download. intel. com/pressroom/kits/press/core 2/Multicore%20 MATS 002%20999%20 pct. pdf

10. 1. 3 Xeon 5000 DP-line (Dempsey) (2) Figure: Packaging of the Dempsey http: //www. tecchannel. de/_misc/img/detail 1000. cfm? pk=342850&fk=432919&id=il-74145482909021379

10. 1. 3 Xeon 5000 DP-line (Dempsey) (3) Figure: The Xeon DP Dempsy with the two FB capable Blackford chipset [1. 2]

10. 1. 3 Xeon 5000 DP-line (Dempsey) (4) (Paxville DP) 5000 (Dempsey) DC DC Xeon DP 2. 8 5030 -5080 Netburst Cores 2*Irwindale dies 2*Cedar Mill dies Intro. 10/2005 5/2006 90 nm 65 nm Die size 2*135 mm 2 2*81 mm 2 Nr. of transistors 2*169 mtrs 2*188 mtrs 2. 8 2. 6 -3. 73 2*2 MB Series Dual/Quad-Core Models Microarchitekture Technology fc [GHz] L 2 FSB [MT/s] 800 667/1066 TDP [W] 135 95/130 PGA 604 LGA 771 Socket EM 64 T HT ED VT EIST La Grande AMT 2 Table: Dual-Core Xeon DP-lines (2) [1. 8], [1. 9]

10. 1. 2 Xeon 5100 DP-line (Woodcrest) (1) Figure: Block diagram of the Merom, Conroe and Woodcrest processors Source: Inkley B. and Tetrick S. , „Intel Multi-core Architecture and implementations, ” IDF, March 2006, http: //download. intel. com/pressroom/kits/press/core 2/Multicore%20 MATS 002%20999%20 pct. pdf

10. 1. 3 Xeon 5100 DP-line (Woodcrest) (2) Woodcrest Figure: Die shot of the Woodcrest (5100 series) processor (L 2: 4 MB) Source: http: //www. intelstartyourengines. com/images/Woodcrest%20 Die%20 Shot%202. jpg

10. 1. 3 Xeon 5100 DP-line (Woodcrest) (3) Merom Conroe Woodcrest Figure: Contrasting the die shots of Merom, Conroe and Woodcrest Sources: Kubicki K. , „Intel 2006 Mobile CPU Roadmap Update, ” Mai 2006, http: //www. dailytech. com/Article. aspx? newsid=2546 Hübner, T. , „Intel Core 2 Duo E 6700 und E 6600, ” July 2006, http: //www. computerbase. de/artikel/hardware/prozessoren/2006/test_intel_core_2_duo_e 6700_e 6600/1/ http: //www. intelstartyourengines. com/images/Woodcrest%20 Die%20 Shot%202. jpg

10. 1. 3 Xeon 5100 DP-line (Woodcrest) (4) (Paxville DP) 5000 (Dempsey) 5100 (Woodcrest) DC DC DC Xeon DP 2. 8 5030 -5080 5110 -5160 Netburst Cores 2*Irwindale dies 2*Cedar dies Single dies Intro. 10/2005 5/2006 6/2006 90 nm 65 nm Die size 2*135 mm 2 2*81 mm 2 143 mm 2 Nr. of transistors 2*169 mtrs 2*188 mtrs 291 mtrs 2. 8 2. 6 -3. 73 1. 6 -3. 0 2*2 MB 4 MB Series Dual/Quad-Core Models Microarchitekture Technology fc [GHz] L 2 FSB [MT/s] 800 667/1066/1333 TDP [W] 135 95/130 65/80 PGA 604 LGA 771 Socket EM 64 T HT ED VT EIST (5140 or above) La Grande AMT 2 Table: Dual-Core Xeon DP-lines (3) [1. 8], [1. 9]

10. 1. 3 Xeon 5300 DP-line (Clovertown) (1) Figure: The Xeon 5300 series (Clovertown) dies are built up of two dual core Woodcrest [1. 4]

10. 1. 3 Xeon 5300 DP-line (Clovertown) (2) Figure: Packaging the Clowertown Source: Wasson S. , „Intel’s Woodcrest procdessor previewed, ” May 2006, http: //techreport. com/etc/2006 q 2/woodcrest/index. x? pg=2

10. 1. 3 Xeon 5300 DP-line (Clovertown) (3) (Paxville DP) 5000 (Dempsey) 5100 (Woodcrest) 5300 (Clovertown) DC DC DC QC Xeon DP 2. 8 5030 -5080 5110 -5160 E 5310 -5345/X 5355 Netburst Cores 2*Irwindale dies 2*Cedar dies Single dies 2*Woodcrest dies Intro. 10/2005 5/2006 6/2006 11/2006 90 nm 65 nm Die size 2*135 mm 2 2*81 mm 2 143 mm 2 2*143 mm 2 Nr. of transistors 2*169 mtrs 2*188 mtrs 291 mtrs 2*291 mtrs 2. 8 2. 6 -3. 73 1. 6 -3. 0 1. 6 -2. 66 2*2 MB 4 MB 2*4 MB Series Dual/Quad-Core Models Microarchitekture Technology fc [GHz] L 2 FSB [MT/s] 800 667/1066/1333 TDP [W] 135 95/130 65/80 80/120 PGA 604 LGA 771 Socket EM 64 T HT ED VT EIST (5140 or above) La Grande AMT 2 Table: Dual-Core Xeon DP-lines (4) [1. 8], [1. 9]

10. 1. 3 Dual/quad-core server processors Dual-Core Xeon MP-lines • Xeon 7000 line Paxville MP 11/2005 90 nm 8/2006 65 nm (Netburst based, multi-chip, two Irwindale dies) • Xeon 7100 line Tulsa (Netburst based, monolithic, Cedar Mill based)

Xeon 7000 line (Paxville MP) (1) 10. 1. 3 Xeon 7000 MP-line (Paxville MP) (1) Series Dual/Quad-Core Models 7000 (Paxville MP) DC 7020 -7041 Microarchitecture Netburst Cores 2*Irwindale dies Intro. 11/2005 Technology 90 nm Die size 2*135 mm 2 Nr. of transistors 2*169 mtrs fc [GHz] L 2 2. 66 -3. 0 2*1/2 MB 1 L 3 FSB [MT/s] TDP [W] Socket 667/800 95/150 PGA 604 EM 64 T HT ED VT EIST La Grande AMT 2 Concerning the L 2 cache size, there is a contradiction in Intel’s documentation; whereas according to the data sheets models of the 7000 series include 1 or 2 MB L 2 caches the comparison charts for all models 1 MB large L 2 caches. 1 Table: Dual-Core Xeon MP-lines (1) [1. 8], [1. 9]

10. 1. 3 Xeon 7100 MP-line (Tulsa) (1) Figure: Block diagram and die shot of Tulsa [1. 5]

10. 1. 3 Xeon 7100 MP-line (Tulsa) (2) Figure: Detailed block diagram of Tulsa (Cedar Mill-based) Source: Inkley B. and Tetrick S. , „Intel Multi-core Architecture and implementations, ” IDF, March 2006, http: //download. intel. com/pressroom/kits/press/core 2/Multicore%20 MATS 002%20999%20 pct. pdf

10. 1. 3 Xeon 7100 MP-line (Tulsa) (3) Figure: Die shot of Tulsa (L 3: 16 M) Source: Vance A. , „Intel completes Operation Catch up with Tulsa release, ” The Register, Aug. 2006, http: //www. theregister. co. uk/2006/08/29/intel_tulsa_out/

10. 1. 3 Xeon 7100 MP-line (Tulsa) (4) Tulsa (435 mm 2) Cedar Mill (81 mm 2) 2 x 2 MB L 2 2 x 1 MB L” + 16 MB L 3 Figure: Contrasting the Cedar Mill and Tulsa die shots Sources: Huynh T. , „Pressler: Intel Extreme Edition 955, ” Dec. 2005, http: //www. sudhian. com/index. php? /articles/show/pressler_intel_extreme_edition_955_prescotts_last_hurrah/ , Vance A. , „Intel completes Operation Catch up with Tulsa release, ” The Register, Aug. 2006, http: //www. theregister. co. uk/2006/08/29/intel_tulsa_out/

10. 1. 3 Xeon 7100 MP-line (Tulsa) (5) 7000 (Paxville MP) 7100 (Tulsa) DC DC 7020 -7041 7110 M-7140 M / 7110 N-7150 N Netburst Cores 2*Irwindale dies Cedar Mill-based single die Intro. 11/2005 8/2006 90 nm 65 nm Die size 2*135 mm 2 435 mm 2 Nr. of transistors 2*169 mtrs 1328 mtrs 2. 66 -3. 0 2. 5 -3. 5 2*1/2 MB 1 2*1 MB Series Dual/Quad-Core Models Microarchitekture Technology fc [GHz] L 2 L 3 4/8/16 MB FSB [MT/s] 667/800 TDP [W] 95/150 PGA 604 Socket EM 64 T HT ED VT EIST La Grande AMT 2 Concerning the L 2 cache size, there is a contradiction in Intel’s dokumentation; whereas according to the data sheets models of the 7000 series include 1 or 2 MB L 2 caches the comparison charts for all models 1 MB large L 2 caches. 1 Table: Dual-Core Xeon MP-lines (2) [1. 8], [1. 9]

10. 1. 3 Guessed road map of Intel processors (1) Category Code Name Cores Cache Market Desktop Kentsfield Dual core multi-die 4 MB Mid 2007 Desktop Conroe Dual core single die 4 MB shared End 2006 Desktop Allendale Dual core single die 2 MB shared End 2006 Desktop Cedar Mill (Net. Burst/P 4) Single core 512 k. B, 1 MB, 2 MB Early 2006 Desktop Presler (Net. Burst/P 4) Dual core, dual die 4 MB Early 2006 Desktop/Mobile Millville Single core 1 MB Early 2007 Mobile Yonah 2 Dual core, single die 2 MB Early 2006 Mobile Yonah 1 Single core 1/2 MB Mid 2006 Mobile Stealey Single core 512 k. B Mid 2007 Mobile Merom Dual core, single die 2/4 MB shared End 2006 Enterprise Sossaman Dual core, single die 2 MB Early 2006 Enterprise Woodcrest Dual core, single die 4 MB Mid 2006 Enterprise Clovertown Quad core, multi-die 4 MB Mid 2007 Enterprise Dempsey (Net. Burst/Xeon) Dual core, dual die 4 MB Mid 2006 Enterprise Tulsa Dual core single die 4/8/16 MB End 2006 Enterprise Whitefield Quad core single die 8 MB, 16 MB shared Early 2008 Figure 5. 7: Future 65 nm processors (Overview) Source: P. Schmid: Top Secret Intel Processor Plans Uncovered www. tomshardware. com/2005/12/04/top_secret_intel_processor_plans_uncovered

10. 1. 3 Guessed road map of Intel processors (1) Codename Cores Cache Market Desktop Wolfdale Dual core, single die 3 MB shared 2008 Desktop Ridgefield Dual core single die 6 MB shared 2008 Desktop Yorkfield 8 cores multi-die 12 MB shared 2008+ Desktop Bloomfield Quad core, single die - 2008+ Desktop/Mob Perryville ile Single core 2 MB 2008 Mobile Penryn Dual core single die 3 MB, 6 MB shared 2008 Mobile Silverthorne - - 2008+ Enterprise Hapertown 8 cores multi-die 12 MB shared 2008 Figure 5. 8: Future 45 nm processors (overview) Source: P. Schmid: Top Secret Intel Processor Plans Uncovered www. tomshardware. com/2005/12/04/top_secret_intel_processor_plans_uncovered

10. 1 Published road map of Intel processors Figure: Roadmap of Intel’s lines Source: Thrax, „ Core 2 Duo and the future of Intel, ” Nov. 2006, http: //www. short-media. com/review. php? r=343

10. 1. 4 Dual/quad-core Itanium processors Dual/quad-core Itanium 2 lines • Dual-core Itanium 2 Montecito 7/2006 90 nm 2008 65 nm (Itanium 2 based, monolithic) • Quad-core Itanium 2 Tukwila (Itanium 2 based, monolithic)

10. 1. 4 Dual-core Itanium 2 (Montecito) (1) Figure: Block diagram and basic floor plan of the Montecito [1. 5]

10. 1. 4 Dual-core Itanium 2 (Montecito) (2) Figure: Block diagram of the Itanium 2 processor [1. 12]

10. 1. 4 Dual-core Itanium 2 (Montecito) (3) Figure: Block diagram of the Montecito Mc. Nairy C. and Bhatia R. , „Montecito, ” IEEE Micro, March-April 2005, pp. 10 -20

10. 1. 4 Dual-core Itanium 2 (Montecito) (4) Figure: New features of Montecito Source: Intel

10. 1. 4 Dual-core Itanium 2 (Montecito) (5) Core Figure: Floor plan of Montecito [1. 14]

10. 1. 4 Dual-core Itanium 2 (Montecito) (6) Madison (130 nm) Montecito (90 nm) (Inthe figure reduced to 90 nm) L 2: 256 KB, L 3: 9 MB L 2 I: 1 MB, L 2 D: 256 KB, L 3: 12 MB Figure: Contrasting Itanium 2 Madison and Montecito (at the same feature size) [1. 14] Further source: Krewell K. , „Best Servers of 2004, ” Microprocessor Report, Jan. 2005, http: //h 10018. www 1. hp. com/wwsolutions/misc/docs/2004_Server_Processor_of_Year. pdf

10. 1. 4 Dual-core Itanium 2 (Montecito) (7) Figure: Contrasting die sizes and floor plans of Itanium processors Source: De. Mone P. , Sizing Up the Super hevyweights, ” Real World Technologies, Sept. 2004, http: //h 21007. www 2. hp. com/dspp/files/unprotected/Itanium/sizingsuperheavys. pdf

10. 1. 4 Dual-core Itanium 2 (Montecito) (8) Dual-Core Itanium 2 (Montecito) Series Models 9010 9015 9020 9030 9040 9050 1. 6 Stepping Introduced 7/2006 Technology 90 nm Die size 596 mm 2 Nr. of transistors 1720 mtrs fc [GHz] 1. 6 1. 40 L 2 1 MB I$ + 256 KB D$ per core L 3 f 1. 42 2*3 MB 2*6 MB 2*4 MB 2*9 MB 2*12 MB 400 533 533 104 104 104 HT FSB (16 B wide) TDP [W] Socket [MT/s] 75 PAC 611 64 -bit HT ED VT (Silvervale) Cache safe EIST DBS Table: Main features of the dual-core Itanium 2 line [1. 8], [1. 9]

10. 1. 5 Quad-core Itanium 2 (Tukwila) (1) Figure: Expected features of the quad-core Tukwila [1. 8]

10. 1. 5 Quad-core Itanium 2 (Tukwila) (2) Figure: Preliminary die shot of Tukwila [1. 11]

10. 1 Literature (1) x 86 multicore processors [1. 1] Bhandarkar D. „Energy Efficient Performance: The Next Frontier, ” Oct. 2006, http: //download. intel. com/technology/eep/fall_microprocessor_forum_2006. pdf [1. 2] Brookwood N. , The Role of intellignet Desing in the Evolution of Multi-Core Processors, ” Febr. 2006. http: //www. insight 64. com/downloads/Intelligent. Design. pdf [1. 3] Douglas J. , „Intel 8 xx series and Paxville Xeon-MP Microprocessors, ” http: //www. hotchips. org/archives/hc 17/3_Tue/HC 17. S 8 T 1. pdf [1. 4] Li W. and Babayan B. , „Extracting The Most Out Of Intel’s Multi-Core Platforms with Software, ” http: //idfemea. intel. com/moscow/download/keynotes_and_tis/Li_Babayan_en. pdf [1. 5] Rusu S. , „Circuit Technologies for Multi-Core Processor Design, ” April 2006, http: //www. ewh. ieee. org/r 6/scv/ssc/April 06. pdf [1. 6] Shimpi A. L. and Wilson D. , Intel Pentium 4 6 xx and 3. 73 EE, ” Febr. 2005, http: //www. anandtech. com/cpuchipsets/showdoc. aspx? i=2353&p=3 [1. 7] Smith, S. L. and Valentine, B. : ”Intel Core Microarchitecture, ” March 2006, http: //download. intel. com/pressroom/kits/press/core 2/ NGMA%20 IDF%20 Press%20 Mar%208%20 PDF%20 Set. pdf [1. 8] - Related Intel Datasheets, http: //www. intel. com/design [1. 9] - Wikipedia

10. 1 Literature (2) Montecito [1. 10] De. Mone P. , Sizing Up the Super hevyweights, ” Real World Technologies, Sept. 2004, http: //h 21007. www 2. hp. com/dspp/files/unprotected/Itanium/sizingsuperheavys. pdf [1. 11] Hoyler G. , „Intel Itanium Architecture Roadmap and Technology Update, ” 2004, http: //www. decus. de/sig/vms/TUD_2004/INTEL. PDF [1. 12] Mc. Nairy C. and Soltis D. „ Itanium 2 Processor Microarchitecture, ” IEEE Micro, March-April 2003, pp. 44 -55 [1. 13] Mc. Nairy C. and Bhatia R. , „Montecito: A Dual-Core, Dual-Thread Itanium Processor, ” IEEE Micro, March-April 2005, pp. 10 -20 [1. 14] Naffziger S. et al. , „The Implementation of a 2 -core Multi-Threaded Itanium-Family Processor, ” Proc. ISSCC, 2005, pp. 182 -183, [1. 15] Naffziger S. et al. , The Implementation of a 2 -Core, Multi-threaded Itanium Family Processor, IEEE Journal Solid-State Circuits, Vol. 41, No. 1, Jan. 2006, pp. 197 -209 [1. 16] Rusu S. , „Circuit Technologies for Multi-Core Processor Design, ” April 2006, http: //www. ewh. ieee. org/r 6/scv/ssc/April 06. pdf [1. 17] - „Inside the Intel Itanium 2 Processor, ” Technical White Paper, July 2002, HP Corp. [1. 18] - Related Intel Datasheets, http: //www. intel. com/design/itanium 2/documentation. htm