Tandem PCIePROM Configuration timing measurement on ZCU 106

Tandem PCIe/PROM Configuration timing measurement on ZCU 106 • Test environment • • 1 Vivado 2018. 3 ZCU 106 production board QSPI SCLK is set to 150 MHz Reduced the FSBL debug print message © Copyright 2020 Xilinx

Steps to speed up boot time to meet PCIe 100 ms requirement for Tandem PROM configuration • Vivado setting for Tandem PROM Configuration • PS: QSPI reference clock Frequency • PL: PCIe(xdma) setting • Modify FSBL • QSPI divider setting • Two-stage separate bitstream configuration support • ZCU 106 Jumper setting The resolution is to use two separate bitstreams for 1 st stage and 2 nd stage. 1 st • stage PL configuration canconfiguration meet the 100 ms PCIe requirement Improved Tandemtiming PROM timing 2 © Copyright 2020 Xilinx

Change QSPI reference clock frequency to 300 MHz 3 © Copyright 2020 Xilinx

Set Tandem Configuration to Tandem PROM 4 © Copyright 2020 Xilinx

Add following property to XDC file to generate two-stage separate bitstream 5 © Copyright 2020 Xilinx

Change divider value to achieve 150 MHz SCLK XQSPIPSU_CLK_PRESCALE_8→_2 QSPI SCLK = QSPI reference clock/divider = 300 MHz/2 = 150 MHz 6 © Copyright 2020 Xilinx

xfsbl_main. c: Reduce debug print message 7 © Copyright 2020 Xilinx

Modify xfsbl_partition_load. c to support two stages bitstream Insert the highlight part 8 © Copyright 2020 Xilinx

xfsbl_bs. c: 9 Insert highlight part © Copyright 2020 Xilinx

xfsbl_bs. c: 10 Modify the highlight part © Copyright 2020 Xilinx

SDK xfsbl_bs. h: 11 Insert highlight part © Copyright 2020 Xilinx

ZCU 106: Reduce the PS_POR_B delay 400 ms delay is added by the Power control chip Open the J 20, J 21 Jumper to reduce 400 ms delay 12 © Copyright 2020 Xilinx

SDK: Create Boot Image 13 © Copyright 2020 Xilinx

SDK: Two separate bitstreams are used, one for 1 st stage another for 2 nd stage 14 © Copyright 2020 Xilinx