Tackling the search for Lepton Flavor Violation with

Tackling the search for Lepton Flavor Violation with GHz waveform digitizing using the DRS chip Stefan Ritt Paul Scherrer Institute, Switzerland

Agenda MEG Experiment searching for m e g down to 10 -13 DRS 1 DRS 2 DRS 3 Feb. 26 th, 2008 Fermilab 2

Motivation Why should we search for m e g ?

The Standard Model Fermions (Matter) u t up charm top photon d s b g down strange bottom ne nm nt Leptons electron neutrino muon neutrino tau neutrino e m t electron Feb. 26 th, 2008 g I muon II tau III Fermilab gluon W W boson Z Z boson Force carriers Quarks Generation c Bosons Higgs* boson *) Yet to be confirmed 4

The success of the SM • The SM has been proven to be extremely successful since 1970’s • Simplicity (6 quarks explain >40 mesons and baryons) • Explains all interactions in current accelerator particle physics • Predicted many particles (most prominent W, Z ) • Limitations of the SM • Currently contains 19 (+10) free parameters such as particle (neutrino) masses • Does not explain cosmological observation such as Dark Matter and Matter/Antimatter Asymmetry Today’s goal is to look for physics beyond the standard model Feb. 26 th, 2008 Fermilab CDF 5

Beyond the SM Find New Physics Beyond the SM High Energy Frontier High Precision Frontier • Produce heavy new particles directly • Heavy particles need large colliders • Complex detectors • Look for small deviations from SM (g-2)m , CKM unitarity • Look forbidden decays • Requires high precision at low energy Feb. 26 th, 2008 Fermilab 6

The Muon Seth Neddermeyer • Discovery: 1936 in cosmic radiation ne • Mass: 105 Me. V/c 2 • Mean lifetime: 2. 2 ms W- e. Carl Anderson ≈ 100% m- nm 0. 014 < 10 -11 led to Lepton Flavor Conservation as “accidental” symmetry Feb. 26 th, 2008 Fermilab 7

LFV and Neutrino Oscillations Neutrino mass m e g possible even in the SM g W- m- nm ne e- LFV in the charged sector is forbidden in the Standard Model n mixing Feb. 26 th, 2008 Fermilab 8

LFV in SUSY • While LFV is forbidden in SM, it is possible in SUSY g W- m- nm e- ne g ≈ 10 -12 m- e- Current experimental limit: BR(m e g) < 10 -11 Feb. 26 th, 2008 Fermilab 9

History of LFV searches cosmic m • Long history dating back to 1947! 10 -1 • Best present limits: • 1. 2 x 10 -11 (MEGA) 10 -3 • m. Ti → e. Ti < 7 x 10 -4 • m → eee < 1 x 10 -13 m→eg m. A → e. A m → eee 10 -2 (SINDRUM II) 10 -12 (SINDRUM II) • MEG Experiment aims at 10 -13 10 -5 stopped p 10 -6 10 -7 m beams 10 -6 • Improvements linked to advance in technology stopped m 10 -9 10 -10 10 -11 SUSY SU(5) BR(m e g) = 10 -13 m. Ti e. Ti = 4 x 10 -16 BR(m eee) = 6 x 10 -16 Feb. 26 th, 2008 10 -12 10 -13 MEG 10 -14 10 -15 1940 Fermilab 1950 1960 1970 1980 1990 2000 2010 10

Current SUSY predictions ft(M)=2. 4 m>0 Ml=50 Ge. V 1) current limit MEG goal tan b “Supersymmetric parameterspace accessible by LHC” 1) 2) J. Hisano et al. , Phys. Lett. B 391 (1997) 341 MEGA collaboration, hep-ex/9905013 Feb. 26 th, 2008 W. Buchmueller, DESY, priv. comm. Fermilab 11

Experimental Method How to detect m e g ?

Decay topology m e g m eg 52. 8 Me. V N g m 52. 8 Me. V 180º 10 e 20 30 40 50 60 Eg[Me. V] N 52. 8 Me. V m • • • → e g signal very clean Eg = Ee = 52. 8 Me. V qge = 180º e and g in time 52. 8 Me. V 10 Feb. 26 th, 2008 Fermilab 20 30 40 50 60 Ee[Me. V] 13

“Accidental” Background m eg g Background g g n m e nn m m n e Annihilation in flight 180º e e n m m e nn n m • • • → e g signal very clean Eg = Ee = 52. 8 Me. V qge = 180º e and g in time Feb. 26 th, 2008 Good energy resolution Good spatial resolution Excellent timing resolution Good pile-up rejection Fermilab 14

Previous Experiments DEe/Ee %FWH M DEg /Eg %FWH M Dteg (ns ) Dqeg (mra d) Inst. Stop rate (s-1) Duty cycle (%) 197 7 8. 7 9. 3 1. 4 - (4. . 6) x 105 100 < 1. 0 10 - 197 7 10 8. 7 6. 7 - 2 x 105 100 < 3. 6 10 - Exp. / Lab Author Yea r SIN (PSI) A. Van der Schaaf P. TRIUM Depommie F r Result 9 9 LANL W. W. Kinnison 197 9 8. 8 8 1. 9 37 2. 4 x 105 6. 4 < 1. 7 10 - Crystal Box R. D. Bolton 198 6 8 8 1. 3 87 4 x 105 (6. . 9) < 4. 9 10 - MEGA M. L. Brooks 199 9 1. 2 4. 5 1. 6 17 2. 5 x 108 (6. . 7) < 1. 2 10 - ? ? ? ~ 10 -13 MEG 10 11 11 How can we achieve a quantum step in detector technology? Feb. 26 th, 2008 Fermilab 15

Collaboration ~70 People (40 FTEs) from five countries Feb. 26 th, 2008 Fermilab 16

Paul Scherrer Institute Proton Accelerator Swiss Light Source Feb. 26 th, 2008 Fermilab 17

PSI Proton Accelerator Feb. 26 th, 2008 Fermilab 18

MEG beam line Rm ~ 1. 1 x 108 m+/s at experiment e+ m+ s ~ 10. 9 mm m+ Feb. 26 th, 2008 Fermilab 19

Liquid Xenon Calorimeter • Calorimeter: Measure g Energy, Position and Time through scintillation light only • Liquid Xenon has high Z and homogeneity Refrigerator • Extremely high purity necessary: 1 ppm H 20 absorbs 90% of light • Currently largest LXe detector in the world: Lots of pioneering work necessary Feb. 26 th, 2008 Fermilab Signals Cooling pipe • ~900 l (3 t) Xenon with 848 PMTs (quartz window, immersed) • Cryogenics required: -120°C … -108° H. V. Vacuum g Liq. Xe for thermal insulation Al Honeycomb window m PMT Plasticfiller 1. 5 m 20

• Use GEANT to carefully study detector • Optimize placement of PMTs according to MC results Feb. 26 th, 2008 Fermilab 21

The complete MEG detector Feb. 26 th, 2008 Fermilab 22

Current resolution estimates Exp. / Lab Author Yea DEe/Ee r %FW HM DEg /Eg %FWH M Dteg (ns) Dqeg (mra d) Inst. Stop rate (s-1) Duty cycl e (%) Result SIN (PSI) A. Van der Schaaf 197 7 8. 7 9. 3 1. 4 - (4. . 6) x 105 100 < 1. 0 10 -9 TRIUM F P. Depommi er 197 7 10 8. 7 6. 7 - 2 x 105 100 < 3. 6 10 -9 LANL W. W. Kinnison 197 9 8. 8 8 1. 9 37 2. 4 x 105 6. 4 < 1. 7 10 - Crystal Box R. D. Bolton 198 6 8 8 1. 3 87 4 x 105 (6. . 9) < 4. 9 10 - MEGA M. L. Brooks 199 9 1. 2 4. 5 1. 6 17 2. 5 x 108 (6. . 7) < 1. 2 10 - 200 8 0. 8 4. 3 0. 18 18 MEG Feb. 26 th, 2008 Fermilab 3 x 107 100 10 11 11 ~ 10 -13 23

MEG Current Status • Goal: Produce “significant” result before LHC • R & D phase took longer than anticipated http: //meg. psi. ch • Detector has been completed by the end of 2007 • Expected sensitivity in 2008: 2 x 10 -12 (current limit: 1 x 10 -11) 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 Feb. 26 th, 2008 R&D Set-up Engineering Data Taking Fermilab 24

Pile-up in the DC system • Pile-up can severely degrade the experiment performance ( MEGA Experiment) ! • Traditional electronics cannot detect pile-up TDC Discriminator Measure Time hits Amplifier Need full waveform digitization > 100 MHz to reject pile-up Moving average baseline Feb. 26 th, 2008 Fermilab 25

Beam induced background 108 m/s produce 108 e+/s produce 108 g/s Cable ducts for Drift Chamber Feb. 26 th, 2008 Fermilab 26

Pile-up in the LXe calorimeter n PMT sum 0. 511 Me. V m eg radiative muon decay 50 51. 5 Me. V 51 52 (m enn)2 + g g m e e m Feb. 26 th, 2008 E[Me. V] ~100 ns t • g’s hitting different parts of LXe can be separated if > 2 PMTs apart (15 cm) • Timely separated g’s need waveform digitizing > 300 MHz • If waveform digitizing gives timing <100 ps, no TDCs are needed Fermilab 27

Requirements summary • Need 500 MHz 12 bit digitization for Drift Chamber system • Need 2 GHz 12 bit digitization for Xenon Calorimeter + Timing Counters • Need 3000 Channels • At affordable price Solution: Develop own “Switched Capacitor Array” Chip Feb. 26 th, 2008 Fermilab 28

The Domino Principle 0. 2 -2 ns Inverter “Domino” ring chain IN Waveform stored Clock Shift Register Out FADC 33 MHz “Time stretcher” GHz MHz Keep Domino wave running in a circular fashion and stop by trigger Domino Ring Sampler (DRS) Feb. 26 th, 2008 Fermilab 29

Switched Capacitor Array • Cons Dt Dt Dt • No continuous acquisition • No precise timing • External (commercial) FADC needed • Pros • High speed (~5 GHz) high resolution (~12 bit equiv. ) • High channel density (12 channels on 5 x 5 mm 2) • Low power (10 m. W / channel) • Low cost (< 100$ / channel incl. VME board) Feb. 26 th, 2008 Fermilab 30

Folded Layout Linear inverter chain causes non-linearity Feb. 26 th, 2008 Fermilab 31

“Tail Biting” speed enable 1 2 3 4 Feb. 26 th, 2008 Fermilab 32

Sample readout DRS 1 Tiny signal 20 p. F 0. 2 p. F I DRS 2 ~k. T Temperature Dependence DRS 3 Feb. 26 th, 2008 Fermilab 33

DRS 3 • Fabricated in 0. 25 mm 1 P 5 M MMC process (UMC), 5 x 5 mm 2, radiation hard • 12 ch. each 1024 bins, 6 ch. 2048, …, 1 ch. 12288 • Sampling speed 10 MHz … 5 GHz • Readout speed 33 MHz, multiplexed or in parallel • 50 prototypes received in July ‘ 06 Feb. 26 th, 2008 Fermilab 34

VME Board USB adapter board 32 channels input 40 MHz 12 bit FADC General purpose VPC board built at PSI Feb. 26 th, 2008 Fermilab 35

Bandwidth + Linearity Readout chain shows excellent linearity from 0. 1 V … 1. 1 V @ 33 MHz readout Analog Bandwidth is currently limited by high resistance of on-chip signal bus, will be increased significantly with DRS 4 0. 5 m. V max. Feb. 26 th, 2008 450 MHz (-3 d. B) Fermilab 36

Signal-to-noise ratio “Fixed pattern” offset error of 5 m. V RMS can be reduced to 0. 35 m. V by offset correction in FPGA SNR: 1 V linear range / 0. 35 m. V = 69 d. B (11. 5 bits) Offset Correction Feb. 26 th, 2008 Fermilab 37

12 bit resolution <8 bits effective resolution 11. 5 bits effective resolution Feb. 26 th, 2008 Fermilab 38

Sampling speed • Unstabilized jitter: ~70 ps / turn • Temperature coefficient: 500 ps / ºC ~200 psec PLL Vspeed Reference Clock (1 -4 MHz) R. Paoletti, N. Turini, R. Pegna, MAGIC collaboration Feb. 26 th, 2008 Fermilab 39

How far can we go? • Maximal sampling speed with current technologies • DRS 4: 5. 5 GHz in favor of linearity and flexibility • 0. 250 mm technology maximum: 8 GHz • 0. 130 mm technology maximum: 15 GHz • Timing in O(10 ps) region is tough • Sampling has to be close to source (cable effect) • TDCs can work in this region (vernier method), but what about discriminator? • Probably only possible with analog sampling first electrons noise Feb. 26 th, 2008 threshold level timing jitter Fermilab 40

Timing Reference domino wave signal 8 inputs 20 MHz Reference clock PMT hit shift register Domino stops after trigger latency MUX • Calibrate inter-cell Dt’s for each chip • 200 ps uncertainty using PLL • 25 ps uncertainty for timing relative to edge Feb. 26 th, 2008 Fermilab 41

What timing can be obtained? • Detailed studies by G. Varner 1) for LAB 3 chip • Bin-by-bin calibration using a 500 MHz sine wave • Accuracy after calibration: 20 ps 1 ns 1) G. Varner et al. , Nucl. Instrum. Meth. A 583, 447 (2007) Feb. 26 th, 2008 Fermilab 42

On-chip PLL loop filter Simulation: DRS 4 PLL Vspeed Reference Clock fclk = fsamp / 2048 Feb. 26 th, 2008 • On-chip PLL should show smaller phase jitter • If <100 ps, no clock calibration required Fermilab 43

Comparison with other chips MATACQ D. Breton LABRADOR G. Varner DRS 3 Bandwidth (-3 db) 300 MHz > 1000 MHz 450 MHz Sampling frequency 1 or 2 GHz 10 MHz … 3. 5 GHz 10 MHz … 5 GHz Full scale range ± 0. 5 V +0. 4 … 2. 1 V +0. 1 … 1. 1 V Effective #bits 12 bit 10 bit 12 bit Sample points 1 x 2520 9 x 256 12 x 1024 Channel per board 4 N/A 32 Digitization 5 MHz N/A 33 MHz Readout dead time 650 ms 150 ms 3 ms – 370 ms Integral nonlinearity ± 0. 1 % ± 0. 05% Radiation hard No No Yes (chip) Board V 1729 (CAEN) - planned (CAEN) Feb. 26 th, 2008 Fermilab 44

Waveform Analysis What can we learn from acquired waveforms?

On-line waveform display S 848 PMTs “virtual oscilloscope” template fit click pedestal histo Feb. 26 th, 2008 Fermilab 46

QT Algorithm original waveform t Region for pedestal evaluation integration area • Inspired by H 1 Fast Track Trigger (A. Schnöning, Desy & ETH) • Difference of Samples (= 1 st derivation) • Hit region defined when DOS is above threshold • Integration of original signal in hit region • Pedestal evaluated in region before hit • Time interpolated using maximum value and two neighbor values in LUT 1 ns resolution for 10 ns sampling time smoothed and differentiated (Difference Of Samples) Threshold in DOS Feb. 26 th, 2008 Fermilab 47

Pulse shape discrimination a g Leading edge Feb. 26 th, 2008 Decay time Fermilab AC-coupling Reflections 48

t-distribution ta = 21 ns tg = 34 ns a Waveforms can be clearly distinguished g Feb. 26 th, 2008 Fermilab 49

Coherent noise Si Vi (t) All PMTs Pedestal Charge average integration • Found some coherent low frequency (~MHz) noise • Energy resolution dramatically improved by properly subtracting the sinusoidal background • Usage of “dead” channels for baseline estimation Feb. 26 th, 2008 Fermilab 50

Pileup recognition DT 8 ns DT 50 ns original DT 10 ns DT 100 ns derivative Dt = 15 ns E 1 E 2 MC simulation DT 15 ns Rule of thumb: Pileup can be detected if DT ~ rise-time of signals Feb. 26 th, 2008 Fermilab 51

Crosstalk elimination Crosstalk removal by subtracting empty channel subtract Hit Feb. 26 th, 2008 Hit Fermilab 52

Spurious Noise Problem • Found “sometimes” a high frequency “ring” on all channels • 40 MHz, ~20 m. V, 1 k. Hz repetition • Finally identified the liquid xenon pump as the source • This noise can screw up timing for rare events • Without waveform digitizing, this would have been very hard to debug Feb. 26 th, 2008 Fermilab 53

Template Fit • Determine “standard” PMT pulse by averaging over many events “Template” pb Experiment 500 MHz sampling • Find hit in waveform • Shift (“TDC”) and scale (“ADC”) template to hit • Minimize c 2 • Compare fit with waveform • Repeat if above threshold • Store ADC & TDC values Feb. 26 th, 2008 Fermilab 54

High pass filtering • Get rid of baseline (low frequency) noise • Improve resolution significantly original waveform template fit integration area Feb. 26 th, 2008 Fermilab after optimized high pass FIR filter 55

Baseline Subtraction S - <thr Feb. 26 th, 2008 - S S Latch + + S Latch 12 bit Latch 100 MHz Clock Baseline subtracted signal LUT 12 x 12 Calibrated and linearized signal Baseline Register Fermilab 56

Constant Fraction Discr. Delayed signal Inverted signal Sum + S Latch + Latch 12 bit Latch Clock <0 MULT Feb. 26 th, 2008 & 0 Fermilab 57

Data Reduction • Zero suppression: hit if max. value > n x s(baseline) • Readout window: start / width in respect to trigger • Pile-up flag: Zero-crossings of first derivation • Re-binning 4: 1, 8: 1, 16: 1 • ADC: Numerical integral of hit over baseline • TDC: Only simple threshold (usable to recognize accidentals) and time-overthreshold 0. 5 ns bins 4 ns bins MEG: Applying to 94% of 100 Hz data Keeping only 6 Hz of waveforms TOT Feb. 26 th, 2008 Fermilab 58

Huffman encoding 0 1 -1 2 0 0. 6 0. 2 10 1 110 0. 2 11 1 0. 4 0. 2 Bin. Code Huffman -1 00 110 0 01 0 1 10 10 2 11 111 Diff Bin. Code Huffman 0 01 0 1 10 10 0 01 0 -1 00 110 0 01 0 20 16 S 0 Feb. 26 th, 2008 Diff Fermilab 59

Where to perform waveform analysis? • Switching from ADC/TDC to ~GHz waveform digitization increases amount of data by ~1000 x • Many algorithms suitable for on-board (FPGA) processing • Charge integration and time estimation (“QT”) • Zero-suppression, re-binning, Huffman encoding • Basic pile-up recognition (zero-crossings of derivative) • Algorithms for embedded CPUs or PC farms • Inter-channel cross-talk removal • Template fit (floating point) DRS Feb. 26 th, 2008 FPGA Front End PC Fermilab Off-line Analysis 60

DAQ System Principle Liquid Xenon Calorimeter Drift Chamber Timing Counter Active Splitter LV DS VME pa ra lle lb Trigger Event number Event type us optical link (SIS 3100) Waveform Digitizing Rack PC GBi Trigger Busy t Et Rack PC hern et Switch Rack PC Rack PC Event Builder Feb. 26 th, 2008 Fermilab 61

Multi-threading model Zero-copy ring buffers VME Round-Robin distribution Calibration Thread VME Transfer Thread Collector Thread Calibration Thread Network Calibration Thread Feb. 26 th, 2008 Fermilab 62

Optimal rate with 4 calibration threads Feb. 26 th, 2008 Fermilab 63

DAQ System • Use waveform digitization (500 MHz/2 GHz) on all channels • Waveform pre-analysis directly in online cluster (zero suppression, calibration) using multi-threading • MIDAS DAQ Software • Data reduction: 900 MB/s 5 MB/s • Data amount: 100 TB/year 2000 channels waveform digitizing Feb. 26 th, 2008 DAQ cluster Fermilab 64

Advanced Topics Reduced dead time, integrated triggering

“Residual charge” problem R After sampling a pulse, some residual charge remains in the capacitors on the next turn and can mimic wrong pulses Solution: Clear before write “Ghost pulse” 2% @ 2 GHz Feb. 26 th, 2008 Fermilab clear Implemented in DRS 4 66

ROI readout mode delayed trigger normal stop trigger stop after latency Trigger Delay stop 33 MHz e. g. 100 samples @ 33 MHz 3 us dead time (2. 5 ns / sample @ 12 channels) Feb. 26 th, 2008 readout shift register Patent pending! Fermilab 67

Daisy-chaining of channels Domino Wave Generation 1 Channel 0 – 1024 cells 1 0 Channel 1 – 1024 cells 0 1 Channel 2 – 1024 cells 1 0 0 Channel 3 – 1024 cells 0 1 Channel 4 – 1024 cells 1 0 0 Channel 5 – 1024 cells 0 1 Channel 6 – 1024 cells 1 0 0 Channel 7 – 1024 cells 0 DRS 4 can be partitioned in: 8 x 1024, 4 x 2048, 2 x 4096, 1 x 8192 cells Feb. 26 th, 2008 Fermilab 68

Interleaved sampling delays (200 ps/8 = 25 ps) 5 GSPS * 8 = 40 GSPS G. Varner et al. , Nucl. Instrum. Meth. A 583, 447 (2007) Feb. 26 th, 2008 Fermilab 69

“Almost” Dead time free system CMC 1 16 channel 32 channel VME board MUX CMC 2 One board is active while other board is read out Feb. 26 th, 2008 Fermilab 70

DRS 4 packaging DRS 4 flip-chip DRS 4 DRS 3 5 mm 9 mm 18 mm Feb. 26 th, 2008 Fermilab 71

New generation of FADCs • 8 simultaneous flash ADCs on one chip • Require differential input • DRS 4 has been redesigned with differential output Feb. 26 th, 2008 Fermilab 72

• Using a multiplexer, input signals can simultaneously digitized at 65 MHz and sampled in the DRS 4 trigger DRS MUX • DRS readout (5 GHz samples) though same 8 -channel FADCs analog front end • FPGA can make local trigger (or global one) and stop DRS upon a trigger FADC 12 bit 65 MHz FPGA global trigger bus Trigger an DAQ on same board LVDS SRAM • Multiplexer will be included in DRS 4 No splitter (signal quality!), no dedicated trigger boards, no dedicated scalers Feb. 26 th, 2008 Fermilab 73

“Redefinition of DAQ” Because of the high channel density of the DRS system, it becomes affordable to use waveform digitizing in experiments which today use ADC/TCDs TDC Disc. Scaler ADC Scope Feb. 26 th, 2008 Conventional New AC coupling Baseline subtraction Const. Fract. Discriminator DOS – Zero crossing ADC Numerical Integration DRS ~GHz FADC ~100 MHz Bin interpolation (LUT) TDC Waveform Fitting Scaler (250 MHz) FPGA Scaler (50 MHz) CPU Oscilloscope Waveform sampling 400 $ / channel 100 $ / channel Fermilab 74

Availability • DRS 4 will become available in larger quantities in summer ’ 08 • Chip can be obtained from PSI on a “non-profit” basis • Delivery “as-is” • Reference design (schematics) from PSI • Costs ~ 10 -15$/channel • Costs decrease if we find sell more… • Full VME board can be purchased from CAEN probably end of ’ 08 with firmware for peak sensing ADC, QDC, … • Struck, others, … ? Feb. 26 th, 2008 Fermilab 32 -channel 65 MHz/12 bit digitizer “boosted” by DRS 4 chip to 5 GHz 75

Other experiments using DRS BPM for XFEL@PSI Magic Telescope, Canary Islands 8 chn. with PGA PET scanners MACE Telescope India Feb. 26 th, 2008 Fermilab 76

Conclusions • Switched Capacitor Array techniques has prospects to trigger a quantum step in data acquisition • The DRS chip has been designed with maximum flexibility and can therefore be used in many applications • Collaboration on a scientific basis is very welcome Datasheets, publications: http: //midas. psi. ch/drs Feb. 26 th, 2008 Fermilab 77