Systems Architecture Lecture 13 Integer Multiplication and Division

Systems Architecture Lecture 13: Integer Multiplication and Division Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan Some or all figures from Computer Organization and Design: The Hardware/Software Approach, Third Edition, by David Patterson and John Hennessy, are copyrighted material (COPYRIGHT 2004 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED). Lec 13 Systems Architecture 1

Introduction • Objective: To provide hardware support for MIPS integer multiplication and divide instructions. To understand how to implement multiplication and division in hardware. • Topics – – – Lec 13 Review MIPS ALU design Review integer multiplication and division MIPS integer multiply and divide instructions Multiplication algorithms Division algorithms Multiply/Divide unit Systems Architecture 2

Support for SLT and Overflow Detection Lec 13 Systems Architecture 3

MIPS ALU Lec 13 Systems Architecture 4

MIPS Integer Multiply and Divide • Hi and Lo registers – mfhi – mflo • Signed and unsigned multiply – multu • Divide instructions – divu – quotient is available in Lo and remainder in Hi Lec 13 Systems Architecture 5

Multiplication in Hardware • More complicated than addition – accomplished via shifting and addition • More time and more microchip area • We will look at 3 versions based on a simple algorithm we learned in elementary school: 0010 __x_1011 (multiplicand) (multiplier) • Negative numbers: convert and multiply – there are better techniques, we won’t look at them Lec 13 Systems Architecture

Multiplication Hardware – Algorithm 1 Datapath Lec 13 Control Systems Architecture

Lec 13 Systems Architecture http: //www. cs. rpi. edu/~hollingd/comporg. 2000/Notes/Mult. PDF 8

Multiplication Hardware – Algorithm 2 Datapath Lec 13 Control Systems Architecture 9

Multiplication Hardware – Algorithm 3 Datapath Control Note: Multiplier starts in right half of product. Lec 13 Systems Architecture

Lec 13 Systems Architecture http: //www. cs. rpi. edu/~hollingd/comporg. 2000/Notes/Mult. PDF 11

Fast Multiplication Hardware • • • Unroll the addition “loop” Use 32 32 -bit adders Each adder produces 32 -bits and a carry-out The least significant bit of each intermediate sum is a bit of the product. The other 31 bits and the carry-out are passed along to the next adder. Lec 13 Systems Architecture

Faster Multiplier • Uses multiple adders – Cost/performance tradeoff Can be pipelined Several multiplication performed in parallel 9/21/2021 Chapter 3 — Arithmetic for Computers 13

Division Hardware – Algorithm 1 Lec 13 Systems Architecture 14

Division Hardware – Algorithm 3 Lec 13 Systems Architecture 15

Lec 13 Systems Architecture http: //www. cs. rpi. edu/~hollingd/comporg. 2000/Notes/Mult. PDF 16