Systemlevel verification and Board level verification By SAHANA

System-level verification and Board level verification By, SAHANA V 2 nd sem, Mtech, VLSI design and embedded systems

1. System Ø A system is a collection of independent component modules forming a complex whole Ø Every system is described by its spatial and temporal boundaries, surrounded by and is influenced by its environment, which is described by the structure and purpose and is expressed in the form of functionality Ø A system need not follow physical boundaries

2. System level verification Ø A system is a logical partition composed of independently verified components Ø A system is composed of few reusable components and conatins a subset of an SOC ASIC Ø A system can also be comprised of several ASICs, which are physically located on printed circuit boards (PCB)

2. 1. 1. ASICs on PCB Figure. 2. 1. Logical system partition

Cntd. . . Ø The verification concentrates on interaction Ø Individual components are specified and designed by separate individuals or team, by assuming, how could components interact each other Ø The assumptions made by different individuals, who are prime source of bugs

Cntd. . . Ø System level verification focuses more on the interaction among the independent components, rather than the functionality of each individual component Ø Thus system verification engineer should depend on correct functioning of individual component Ø The functionality can be verified better at the component-level verification

Cntd. . . Ø The testcase defines the system Ø Since the systems are logical partitions comprised of any number of components, regardless of their physical location Ø The testcases that are determined to be interesting and significant, will decide which system to use and verify

Cntd. . . Ø To minimize the simulation overhead, smallest possible system is preferred, to execute the specified testcase Ø Because for very large systems, a set of standard systems should be defined Ø And the same system is used for many testcases, even if in some cases, some of the individual components are not required

2. 2. Board level verification Ø Board level models are generated from the board design tool Ø The primary objective of board level verification is to confirm whether the system captured by the board design tool is correct or not Ø Unlike the logical system model, the model for the board design must be automatically generated by the board capture tool

Cntd. . . Ø While verifying the board design or any other physical partition, one must take care of, which part of the system ahs to be verified and manufactured Ø There should be a direct link between the captured design and simulation results Ø Automatic generation of the board-level model from the capture tool, gives that link Ø A logical system model has no restriction, so it can be manually generated for the system of interest

Cntd. . . Ø Most of the components on the board will not fit in a digital simulation environment Ø The problem with the board level models is obtaining suitable models for all the components Ø For this purpose third-party sources and hardware modelers are used Ø Generating a model out of a board design tool involves introducing approximations

Cntd. . . Ø For example, Analog devices connectors, opto-couplers and other components used in board level designs do not translate easily in a digital simulation environment Ø Board level parasites cannot be modified Ø The generated model may include models for board-level parasitics that may effect the functional correctness of the board Ø As the speed of signals in a board increases, transmission line effects will play a major role Ø ASICs cannot be designed, without considering eventual use on a circuit board