SystemLevel PowerAware Design Techniques in RealTime Systems Osman

System-Level Power-Aware Design Techniques in Real-Time Systems Osman S. Unsal, Israel Koren, System-Level Power-Aware Design Techniques in Real. Time Systems, Proceedings of IEEE, Vol. 91, No. 7, July 2003.

Power Management n Why & What: Power Management? q Rapid growth of worldwide total power dissipation n q q q 87 M CPUs consumed 160 MW in 1992 -> 500 M CPUs consumed 9, 000 MW in 2001 Battery operated: Laptops, PDAs, Cell phones, Wireless Sensors, . . . Heat: Complex Servers (server farms, multiprocessors, etc. ) Power Aware: Maintain Qo. S while reducing energy Source: Daniel Mosse (CS 1651 at Univ. of Pittsburg)

Why System-Level Design? n Power management at various system layers q n Circuit & device level, archiecture & compiler, OS & network design Most existing research regarding poweraware RT systems focus on power-aware RT scheduling q CPU is only a single source of power consumption!

Misconceptions about power-aware design n Power-aware ≠ low-power (minimize power consumption) q n n Delay some instruction execution, e. g. , to reduce peak power -> Executes longer & consumes more power Decreasing average power does not imply decreasing max power Power ≠ energy efficiency q q Energy = ∫power Perf may degrade resulting in more energy consumption

Misconceptions about power-aware design n Power-constrained ≠ energy-constrained q n solar power (infinite source) vs. battery power Energy-constrained systems do not always target energy minimization q q Charge = f(battery capacity, rate of discharge) Goal is battery lifetime extension

Motivations for power-aware design for RT sytems n n n Limited energy-budget & timing constraints, e. g. , in space & multimedia applications Limited form factor & low heat dissipation, e. g. , in avionics, robotics & space missions Often overdesigned to support timing guarantees under the wosrt case q n Tasks do not run until their WCET -> Energy inefficient Fault-tolerance q Reliability via replication -> high power consumption

What is system-level power-aware design? n n n Power-awareness embedded in every step of system design Power-compiler can do instruction scheduling to reduce power consumption OS-level heuristic may scale down f and Vdd Network-level schems may put the network I/F into standby mode Today, we will focus on OS & network levels

OS Level n n n Voltage & frequency scaling I/O devices Power and energy analysis of RTOS Distributed RT systems Soft real-time systems

Power Management n How? q q Power off un-used parts: LCD, disk for Laptop Gracefully reduce the performance n CPU: dynamic power Pd = Cef * Vdd 2 * f [Chandrakasan-1992, Burd-1995] q Cef : switch capacitance q Vdd : supply voltage q f : processor frequency linear related to Vdd Source: Daniel Mosse (CS 1651 at Univ. of Pittsburg)

Power Aware Scheduling n Static Power Management (SPM) q fmax Static Slack T 1 T 2 T 1 -1994, Yao-1995, Gruian 2000] T 1 0. 6 E T 2 T 1 T 2 0. 6 E time fmax/2 T 1 E time Static slack: uniformly slow down all tasks [Weiser Energy idle D f Source: Daniel Mosse (CS 1651 at Univ. of Pittsburg) T 2 E/4 time

Power Aware Scheduling n Dynamic Power Management (DPM) q q n Dynamic slack: non-worst execution 10% [Ernst 1997] DPM: [Krishna-2000, Kumar-2000, Pillai-2001, Shin-2001] Multi-Processor q q SPM: length of schedule over deadline DPM ? ? ? fmax Static Slack T 1 T 2 idle D E time fmax/2 T 1 T 2 E/4 time fmax/2 Dynamic Slack T 1 time fmax/3 T 1 T 2 Source: Daniel Mosse (CS 1651 at Univ. of Pittsburg) 0. 12 E time

References (Power-Aware RT Scheduling) n n n [Chandrakasan-1992] A. P. Chandrakasan and S. Sheng and R. W. Brodersen. Low-Power CMOS Digital Design. IEEE Journal of Solidstate Circuit, V 27, N 4, April 1992, pp 473 --484 [Burd-1995] T. D. Burd and R. W. Brodersen. Energy efficient cmos microprocessor design. In Proc. of The HICSS Conference, pages 288 -297, Maui, Hawaii, Jan. 1995. [Weiser-1994] M. Weiser, B. Welch, A. J. Demers, and S. Shenker. Scheduling for reduced CPU energy. In Operating Systems Design and Implementation, pages 13 -23, 1994 [Yao-1995] F. Yao, A. Demers, and S. Shenker. A scheduling model for reduced cpu energy. In Proc. of The 36 th Annual Symposium on Foundations of Computer Science, pages 374382, Milwaukee, WI, Oct. 1995. [Gruian-2000] F. Gruian. System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage Processors. The Power-Aware Computing Systems 2000 Workshop at ASPLOS 2000, Cambridge, MA, November 2000 [Ernst-1997] R. Ernst and W. Ye. Embedded program timing analysis based on path clustering and architecture classification. In Proc. of The International Conference on Computer-Aided Design, pages 598– 604, San Jose, CA, Nov. 1997. [Krishna-2000] C. M. Krishna and Y. H. Lee. Voltage clock scaling adaptive scheduling techniques for low power in hard real-time systems. In Proc. of The 6 th IEEE Real-Time Technology and Applications Symposium (RTAS 00), Washington D. C. , May. 2000. [Kumar-2000] P. Kumar and M. Srivastava, Predictive Strategies for Low-Power RTOS Scheduling, Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers and Processors [Pillai-2001] P. Pillai and K. G. Shin. Real-Time Dynamic Voltage Scaling for Low-Power Embedded Operating Systems, 18 th ACM Symposium on Operating Systems Principles (SOSP? 1), Banff, Canada, Oct. 2001 [Shin-2001] D. Shin, J. Kim and S. Lee, Intra-Task Voltage Scheduling for Low-Energy Hard Real-Time Applications, IEEE Design and Test of Computers, March 2001 [Zhu-2001] D. Zhu, R. Melhem, and B. Childers. Scheduling with Dynamic Voltage/Speed Adjustment Using Slack Reclamation in Multi-Processor Real. Time Systems, RTSS'01 (Real. Time Systems Symposium), London, England, Dec 2001 152 Source: Daniel Mosse (CS 1651 at Univ. of Pittsburg)

I/O devices n n Much less work has been done compared to VS (voltage scaling) in real-time systems Swaminathan et al [72] q q q Power-aware I/O device scheduling for hard real-time systems Tasks are independent but not periodic A priori knowledge of task schedule & device usage list required

Power & energy analysis of RTOS n Power consumption of μc-OS on Fujitsu SPARClite processor q q n μc-OS: Open-source embedded RT kernel introduced in an earlier lecture for project ideas Evaluate power consumption by system calls [73] μc-OS, Ecnidna, NOS (baseline “bare-bones” scheduler) [74] n n RTOS overheads are two to four times higher than NOS Poorly design idele loops can double the energy consumption

Power & energy analysis of RTOS n Acquaviva [75] q q q Increasing context switch frequency from 0 Hz to 10 Khz does not affect energy consumption -> Context switch mechanism in RTOS is energy efficient More energy is consumed when cache flushing effect during context-switch is considered I/O: CPU sends data bursts > output buffer -> Considerable energy consumption when buffer is full or when it polls a synchronization variable (similar to [74])

Distributed/Multiprocessor realtime systems n Reminder q Tightly coupled multiprocessor system n n q Multiple processors are connected at the bus level and share main memory Extreme: multicore with multiple processors on a chip Loosely coupled multiprocessor system (e. g. , cluster) n Multiple, stand-alone processors connected via, e. g. , Gigabit Ethernet

Distributed/Multiprocessor realtime systems n n Classic RT scheduling ≠ Power-aware one Example: a tightly coupled RT system with 2 processors, 2 memory banks, 1 ready queue q Apply EDF n q Assign a task to the first available processor Put memory bank(s) into sleep mode if not used

Distributed/Multiprocessor realtime systems n n Task set Assume memory utilization is linearly dependent on exec time

Distributed/Multiprocessor realtime systems n Classic Load Balancing (LB) q q n Try to balance memory bank utilization Assign T 1 & T 2 to bank 1 (bank utilization 70%) & T 3 & T 4 to bank 2 (BU 54. 1%) Power-Aware (PA) q q q Assign harmonically related tasks to the same bank Tasks are simultaneously active more often Assign T 1 & T 3 (BU 36. 6%) to bank 1 & T 2 & T 4 to bank 2 (BU 87. 5%)

Distributed/Multiprocessor realtime systems n PA vs. LB Several variations possible: Another project idea!

Soft real-time systems [77] n n Hand-held, pocket computes – audio, video, GPS, . . . Power profile of a pocket computer shows more dynamic power profile than a laptop Using a single JVM is 25% more energy efficient than using one JVM per application Just-in-time compilation is power efficient

Soft real-time systems: Battery lifetime n Energy-aware Qo. S tradeoff [79] q q q n n Energy-aware scheduling favoring low energy & critical tasks Tunable toward extended battery life at the cost of perf Battery life can be extended up to 100% with perf degradation of 40% Open & closed-loop approaches [80] Tight cooperation btwn OS and applications for energy savings [81]

Soft real-time systems: Web server n Web workloads are bursty q q q n n 1998 Nagano Winter Olympic 1840 hits/sec during peak time Only 459 hits/sec in average Voltage scheduling & frequency scheduling during the predicted low activity time -> 23% - 36% energy savings Heat is also a critical factor in this kind of systems

Network Level n Much less work has been done compared to RT scheduling & RTOS q q n Qo. S support for audio & video streaming, e. g. , RSVP (Resource Reseravation Protocol), RTP, RTSP, is a different story ATM: Constant Bit Ratio & Variable Bit Ratio Research issues q q q Limited hard RT support, e. g. , CAN (Control Area Network) Overlay networks? Wireless networks?

Network Level n Wireless communications: Relatively new technologies q Wi. Fi (IEEE 802. 11) q Energy-efficient MAC (Medium Access Control) q Example: S-MAC for Wireless Sensor Networks n In WSNs, duty cycle ≤ 1%; 802. 11 too expensive n Efficient sleep scheduling: If a node loses contention for the medium, it goes to sleep for the duration specified in each packet n RTS/CTS for an entire message that can be multiple packets q n Fairness in WSNs is not as important as other wireless ad hoc networks S-MAC consumes 2 -6 times less energy than 802. 11 [96]

Above the MAC layer n LEACH (Low-Energy Adaptive Clustering Hierarchy) q q n Cluster head/cluster can aggregate data Randomly elect a cluster head RAP & SPEED q q Real-time protocols in WSNs To be discussed later in this class

Shortest path vs. max power reduction Balance timing & power constraints!

Questions?