System components z Timing diagrams z Memory z

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System components z. Timing diagrams. z. Memory. z. Busses and interconnect. © 2000 Morgan

System components z. Timing diagrams. z. Memory. z. Busses and interconnect. © 2000 Morgan Kaufman Overheads for Computers as Components

Timing diagrams z A timing diagram shows a trace through the operation of a

Timing diagrams z A timing diagram shows a trace through the operation of a system. y Generally used for asynchronous machines with timing constraints. enq © 2000 Morgan Kaufman Overheads for Computers as Components ack

Timing diagram syntax z. Constant value: 1 0 z. Stable: z. Changing: z. Unknown:

Timing diagram syntax z. Constant value: 1 0 z. Stable: z. Changing: z. Unknown: © 2000 Morgan Kaufman Overheads for Computers as Components

Timing constraints z. Minimum time between two events: enq 20 ns ack © 2000

Timing constraints z. Minimum time between two events: enq 20 ns ack © 2000 Morgan Kaufman Overheads for Computers as Components

Origin of timing constraints z. Control signals are passed on the bus: D 20

Origin of timing constraints z. Control signals are passed on the bus: D 20 ns c a © 2000 Morgan Kaufman Overheads for Computers as Components Q

Memory device organization n r Memory array c © 2000 Morgan Kaufman Overheads for

Memory device organization n r Memory array c © 2000 Morgan Kaufman Overheads for Computers as Components

Memory parameters z. Size. y. Address width. z. Aspect ratio. y. Data width. ©

Memory parameters z. Size. y. Address width. z. Aspect ratio. y. Data width. © 2000 Morgan Kaufman Overheads for Computers as Components

Types of memory z. ROM: y. Mask-programmable. y. Flash programmable. z. RAM: y. DRAM.

Types of memory z. ROM: y. Mask-programmable. y. Flash programmable. z. RAM: y. DRAM. y. SRAM. © 2000 Morgan Kaufman Overheads for Computers as Components

SRAM vs. DRAM z. SRAM: y. Faster. y. Easier to integrate with logic. y.

SRAM vs. DRAM z. SRAM: y. Faster. y. Easier to integrate with logic. y. Higher power consumption. z. DRAM: y. Denser. y. Must be refreshed. © 2000 Morgan Kaufman Overheads for Computers as Components

Typical generic SRAM CE’ R/W’ Adrs SRAM Data © 2000 Morgan Kaufman Overheads for

Typical generic SRAM CE’ R/W’ Adrs SRAM Data © 2000 Morgan Kaufman Overheads for Computers as Components

Generic SRAM timing CE’ R/W’ Adrs Data From SRAM read © 2000 Morgan Kaufman

Generic SRAM timing CE’ R/W’ Adrs Data From SRAM read © 2000 Morgan Kaufman Overheads for Computers as Components From CPU write time

Generic DRAM device CE’ R/W’ RAS’ CAS’ Adrs DRAM Data © 2000 Morgan Kaufman

Generic DRAM device CE’ R/W’ RAS’ CAS’ Adrs DRAM Data © 2000 Morgan Kaufman Overheads for Computers as Components

Generic DRAM timing CE’ R/W’ RAS’ CAS’ Adrs row adrs col adrs Data ©

Generic DRAM timing CE’ R/W’ RAS’ CAS’ Adrs row adrs col adrs Data © 2000 Morgan Kaufman data Overheads for Computers as Components time

Page mode access CE’ R/W’ RAS’ CAS’ Adrs Data © 2000 Morgan Kaufman row

Page mode access CE’ R/W’ RAS’ CAS’ Adrs Data © 2000 Morgan Kaufman row adrs col adrs data Overheads for Computers as Components col adrs data time

RAM refresh z. Value decays in approx. 1 ms. z. Refresh value by reading

RAM refresh z. Value decays in approx. 1 ms. z. Refresh value by reading it. y. Can’t access memory during refresh. z. CAS-before-RAS refresh. z. Hidden refresh. © 2000 Morgan Kaufman Overheads for Computers as Components

Other types of memory z. Extended data out (EDO): improved page mode access. z.

Other types of memory z. Extended data out (EDO): improved page mode access. z. Synchronous DRAM: clocked access for pipelining. z. Rambus: highly pipelined DRAM. © 2000 Morgan Kaufman Overheads for Computers as Components

Flash issues z. Flash is programmed at system voltages. z. Erasure time is long.

Flash issues z. Flash is programmed at system voltages. z. Erasure time is long. z. Must be erased in blocks. © 2000 Morgan Kaufman Overheads for Computers as Components

Generic bus structure z. Address: m n z. Data: z. Control: © 2000 Morgan

Generic bus structure z. Address: m n z. Data: z. Control: © 2000 Morgan Kaufman c Overheads for Computers as Components

Electrical bus design z Bus signals are usually tri-stated. z Address and data lines

Electrical bus design z Bus signals are usually tri-stated. z Address and data lines may be multiplexed. z Every device on the bus must be able to drive the maximum bus load: y. Bus wires. y. Other bus devices. z Bus may include clock signal. y. Timing is relative to clock. © 2000 Morgan Kaufman Overheads for Computers as Components

Four-cycle handshake 3 1 enq data 4 2 ack © 2000 Morgan Kaufman Overheads

Four-cycle handshake 3 1 enq data 4 2 ack © 2000 Morgan Kaufman Overheads for Computers as Components

Busses as communicating machines enq = 1 ack = 0 0 enq 1 1

Busses as communicating machines enq = 1 ack = 0 0 enq 1 1 enq = 0 ack = 1 1 enq 0 M 1 © 2000 Morgan Kaufman 0 0 M 2 Overheads for Computers as Components 1

When should you handshake? z. When response time cannot be guaranteed in advance: y.

When should you handshake? z. When response time cannot be guaranteed in advance: y. Data-dependent delay. y. Component variations. © 2000 Morgan Kaufman Overheads for Computers as Components

Fixed-delay memory access read = 1 adrs = A R/W data R/W R reg

Fixed-delay memory access read = 1 adrs = A R/W data R/W R reg = data adrs mem[adrs] = data = mem[adrs] memory CPU © 2000 Morgan Kaufman W Overheads for Computers as Components

Variable-delay memory access read = 1 adrs = A R/W done = 0 data

Variable-delay memory access read = 1 adrs = A R/W done = 0 data done n y reg = data adrs done R/W R data = mem[adrs] done = 1 memory CPU © 2000 Morgan Kaufman W mem[adrs] = data done = 1 Overheads for Computers as Components

Typical bus access clock R/W’ Address enable adrs Data Ready’ data write time read

Typical bus access clock R/W’ Address enable adrs Data Ready’ data write time read © 2000 Morgan Kaufman Overheads for Computers as Components

Bus mastership z. Bus master controls operations on the bus. z. CPU is default

Bus mastership z. Bus master controls operations on the bus. z. CPU is default bus master. z. Other devices may request bus mastership. y. Separate set of handshaking lines. y. CPU can’t use bus when it is not master. © 2000 Morgan Kaufman Overheads for Computers as Components

Direct memory access (DMA) z. DMA provides parallelism on bus by controlling transfers without

Direct memory access (DMA) z. DMA provides parallelism on bus by controlling transfers without CPU. I/O memory CPU DMA © 2000 Morgan Kaufman Overheads for Computers as Components

DMA operation z CPU sets up DMA transfer: y. Start address. y. Length. y.

DMA operation z CPU sets up DMA transfer: y. Start address. y. Length. y. Transfer block length. y. Style of transfer. z DMA controller performs transfer, signals when done: y. Cycle-stealing. y. Priority. © 2000 Morgan Kaufman Overheads for Computers as Components

Power. PC busses © 2000 Morgan Kaufman Overheads for Computers as Components

Power. PC busses © 2000 Morgan Kaufman Overheads for Computers as Components

USB 2. 0 z. Goals: y. Easy to use. y. Low cost for consumer

USB 2. 0 z. Goals: y. Easy to use. y. Low cost for consumer devices. y. Up to 480 Mb/s. y. Real-time audio, video. y. Both isochronous and asynchronous communication. © 2000 Morgan Kaufman Overheads for Computers as Components

USB architecture Bus topology. Stack. Data flow model. Schedule. host interconnect device © 2000

USB architecture Bus topology. Stack. Data flow model. Schedule. host interconnect device © 2000 Morgan Kaufman Overheads for Computers as Components

Bus tiers Device = {hub, function} hub function host function Tier 1 © 2000

Bus tiers Device = {hub, function} hub function host function Tier 1 © 2000 Morgan Kaufman tier 2 tier 3 Overheads for Computers as Components tier 4 …. tier 7

USB signaling z. Speeds: y. High-speed is 480 Mb/s. y. Full-speed is 12 Mb/s.

USB signaling z. Speeds: y. High-speed is 480 Mb/s. y. Full-speed is 12 Mb/s. y. Low-speed is 1. 5 Mb/s. z. Signals: y. Vbus, Gnd. y. D+, D-. © 2000 Morgan Kaufman Overheads for Computers as Components

USB power z. USB devices can pull a limited amount of power from the

USB power z. USB devices can pull a limited amount of power from the bus. y. May also supply their own power. z. System may provide a powermanagement protocol. y. Independent of USB. © 2000 Morgan Kaufman Overheads for Computers as Components

USB bus protocol z. Polled bus, all transfers initiated by host. z. Basic transaction:

USB bus protocol z. Polled bus, all transfers initiated by host. z. Basic transaction: y. Host sends token packet: x. Type and direction. x. USB device number. x. Endpoint number (subdevice). y. Data transfer packet. y. Acknowledge packet. © 2000 Morgan Kaufman Overheads for Computers as Components

Robustness z. Error detection/correction. z. Automatic handling of device attach/detach. z. Self-recovery in protocol.

Robustness z. Error detection/correction. z. Automatic handling of device attach/detach. z. Self-recovery in protocol. z. Streaming data management. z. Pipes for data management. © 2000 Morgan Kaufman Overheads for Computers as Components

USB pipes z. Functions are allocated to data pipes. y. Pipes limit interference between

USB pipes z. Functions are allocated to data pipes. y. Pipes limit interference between functions. z. Bandwidth is allocated among pipes. z. Devices must supply buffer memory. © 2000 Morgan Kaufman Overheads for Computers as Components

USB data flow model z Four types of implementation: y. Device hardware. y. Client

USB data flow model z Four types of implementation: y. Device hardware. y. Client software to connect to application. y. USB system software. y. USB host controller (host side system interface). © 2000 Morgan Kaufman host device Client SW function USB system SW USB logical device USB host controller USB bus interface Overheads for Computers as Components Physical communication

Logical bus topology z. Bus appears to be a simple host/device system: host device

Logical bus topology z. Bus appears to be a simple host/device system: host device © 2000 Morgan Kaufman Overheads for Computers as Components

Client software view z. Each client sees its own function but not the whole

Client software view z. Each client sees its own function but not the whole system: Client SW function © 2000 Morgan Kaufman Overheads for Computers as Components

Endpoints z Each logical device is a collection of endpoints. z Each endpoint is

Endpoints z Each logical device is a collection of endpoints. z Each endpoint is simplex (input or output). z Endpoint description: y. Bus frequency/latency. y. Bandwidth requirement. y. Endpoint number. y. Error handling requirements. y. Maximum packet size. y. Transfer type. y. Transfer direction. © 2000 Morgan Kaufman Overheads for Computers as Components

Pipes z. Two types of pipes: y. Stream. y. Message. z. Pipe description includes:

Pipes z. Two types of pipes: y. Stream. y. Message. z. Pipe description includes: y. Pipe type. y. Direction. y. Bus access and bandwidth. © 2000 Morgan Kaufman Overheads for Computers as Components

Bus transfer types z. Data goes through the pipe in FIFO order. z. Four

Bus transfer types z. Data goes through the pipe in FIFO order. z. Four types of transfers: y. Control. y. Isochronous—periodic data stream. y. Interrupt. y. Bulk—non-periodic, large data transfer. © 2000 Morgan Kaufman Overheads for Computers as Components