Synchronous Digital Design Methodology and Guidelines Digital System

Synchronous Digital Design Methodology and Guidelines Digital System Design

Synchronous Design • All flip-flops clocked by one common clock • Reset only used for initialization • Races and hazards are no problem

Why synchronous design? • Hazard – Problems due to timing that cannot be observed from functional analysis

Timing Hazard • Static hazard: possibility of a brief signal value change when the signal was expected to be stable, due to timing (glitch) • Dynamic hazard: possibility of multiple output transitions caused by a single input transition due to multiple signal paths with different delays

Static Hazard If d is the delay of each gate

Analyzing Static Hazards using Karnaugh maps A static hazard can occur when changing a single input variable causes a jump from one prime implicant to another Solution: include an additional prime implicant

Eliminating hazards using Flip. Flops

Synchronous Design • Three things must be ensured by the designer: – Minimize and determine clock skew – Account for flip-flop setup and hold times – Reliably synchronize asynchronous inputs

Timing Analysis >0 Setup time margin >0 Hold time margin

Clock skew

Example • Determine the maximum frequency of the following circuit with and without skew

Clock Jitter

Clock Gating • Clock gating is done to disable the clock for low power consumption using a clken signal • It is wrong to gate the clock in the following way, instead use a synchronous load (enable) signal

Asynchronous Inputs It is impossible to guarantee setup and hold timing constraints on inputs synchronized with a clock unrelated to the system clock

Asynchronous inputs • Synchronize only in one place

Metastability • Metastability is a phenomenon that may occur if the setup and hold time requirements of the FF are not met, leading in the output settling in an unknown value after unspecified time.

Reliable synchronizer design

Example • Design a synchronizer that synchronizes two inputs async 1 and async 2 generated with a 50 MHz clock CLK 1, to a system with a 33 MHz clock CLK 2 totally independent of CLK 1. Draw appropriate timing diagrams.

Mean-time between failures f: frequency of flip-flop clock a: number of asynchronous input changes per second in flipflop input To, τ: constants depending on flip-flop electrical characteristics Assume a 10 Mhz clock, ts = 20 ns, To = 0. 4 sec, τ = 1. 5 ns and that the asynchronous input can change 100, 000 times per second, then tr = 1/f – ts = 80 ns MTBF(80 ns) = exp(80/1. 5)/0. 4× 10^7× 10^5= 3. 6× 10^11 s

Cascaded synchronizer

Synchronizing bus transfers • Do not use dual f/f synchronizers in all bits, this will only increase the chances of metastability • Synchronize the control signals and read the input when safe to do so

Synchronization circuit

FIFO Synchronizer basic concept • On burst transfers, the receiver cannot afford to wait for the signal to settle. • Solution: A dual-port RAM FIFO • Problem: How do we synchronize the counters?

Summary • In order to avoid hazards and races, synchronous design is used • In synchronous design a single common clock is used and reset is only used for initialization • The only considerations in synchronous design are the flip-flop setup and hold times, clock skew and asynchronous input synchronization • Asynchronous inputs are commonly synchronized using 2 flip-flops clocked with the synchronous system clock • Synchronization should only be done in one place • In bus transfers, synchronize only the control signals or use a FIFO

Design trade-offs

Common design trade-offs • Performance – Latency – Throughput – Delay (timing) • Area – Gates (ASIC) – Flip-flops/LUTs (FPGA) • Power consumption – Dynamic – Static – Leakage

Design for Speed • Design for High Throughput – Definition: High data rate, acceptable latency – Technique: Pipelining • Design for Low Latency – Definition: Output available as soon as possible – Technique: Parallelism, Removal of pipelining • Design for Timing – Definition: High clock speed, low delay between registers – Technique: Add intermediate registers

Example 1: Design for low latency (parallelism) • X=a+b+c+d Delay = 3*add Latency = 1 cycle Throughput = X bits/clock Delay = 2*add Latency = 1 cycle Throughput = X bits/clock

Example 1: Design for delay • X=a+b+c+d Delay = 1*add + Reg Latency = 2 cycles Throughput = X bits/clock

Example 2: Design for delay x=0; for (i=0; i<4; i++) x+= a[i]*b; Delay: 1*Mul + 1 Add Latency: 4 cycles Throughput: X bits/4 cycles

Example 2: Design for latency

Example 2: Design for throughput

Design for Area • Resource (logic) sharing • Rolling up the pipeline

Resource Sharing • Y= C 1* X[0] + C 2 *X[1] + C 3*X[2] • Is it possible to perform all multiplications with a single multiplier? • Is it possible to perform all additions with a single accumulator?

Resource Sharing

Design for low-power • Power components: • Dynamic power consumption (switching): power consumed due to charging and discharging parasitic capacitances on gates and wires • Static power consumption: Power consumed when no switching • Leakage current power consumption:

Design for power • Clock Gating • Dual-edge triggered Flip-Flops • Lowering core voltage

Clock Gating • Clock gating is done to disable the clock for low power consumption using a clken signal • It is wrong to gate the clock in the following way, instead use a synchronous load (enable) signal or a global clock multiplexer (if available)

Dual-Edge Triggered Flip-Flops Single-edge triggered FF Dual-edge triggered FF (same data rate) • Dual-edge triggered flip-flops should only be used if available in the target technology • Otherwise, redundant flip-flops and gating will be used to emulate the desired functionality

Lowering core voltage • Only reduce core voltage within acceptable limits (5 to 10%) • Power consumption in a simple resistor is proportional to the square of the voltage • Keep in mind that performance will degrade too

Review questions/problems • Pipelining will make your circuit – – A. smaller B. exhibit lower latency C. Consume less power D. exhibit higher throughput • Parallelism creates a – – A. latency/throughput trade-off B. Performance/area trade-off C. Area/power consumption trade-off D. performance/power consumption trade-off • Pipeline the following datapath for a three-cycle latency so that you get the maximum operation frequency. How much is the maximum operation frequency?